This paper presents an enhanced path delay fault simulator for combinational circuits. The main objective of this work is to improve the simulation time of path delay fault testing. Our experiments consider K-longest path sets of ISCAS'85 benchmark circuits, and 10M single input change (SIC) test patterns were applied and repeated ten times in order to cover statistical variations. The experimental results show that the modified path selection and simulation algorithm provides good fault coverage and 20% improved simulation time as an average speed-up factor.

Delay faults in content addressable memories (CAMs) is a major concern in many applications such as network routers, IP filters, longest prefix matching (LPM) search engines and cache tags where high speed data search is significant. It creates the need for analysis of critical paths and detecting associated faults using a minimum number of test patterns. This paper proposes a test method to detect critical path delay faults in CAM systems using a newly proposed low power TCAM cell structure. The proposed complement bit walk (CBW) algorithms are using low time complexity such as 3m+n and 2m+2n operations. The fault simulation of the given TCAM system provides 100% fault coverage for the write, search and pseudo logic faults.

This paper presents novel cell structures for fully parallel static type binary content addressable memory (BCAM) with low power and high flexibility. The proposed CAM core cell structures eliminate the drawbacks and adapt the advantages of single bit line and dual bit line cell structures. In this work, the word match line (ML) structure of low power BCAM employs Static pseudo CMOS (SPC) logic. HSPICE simulations for 32×32 and 128×32 BCAM systems were performed under 0.18 mm technology for different cell structures. The result shows that the proposed design provides the power dissipation of 3.94 mW with the delay time of 2.02 ns @ 1.8 V supply voltage. The measurement results of 128×32 PC-BCAM show that the proposed BCAM cell reduces power dissipation by 76% and improves search speed by 65%

A probabilistic power estimation technique for combinational circuits is presented. A novel set of simple waveforms is the kernel of this technique. The transition density of each circuit node is estimated. Existing methods have local glitch filtering approaches that fail to model this phenomenon correctly. Glitches originated from a node may be filtered in some, but not necessarily all, of its successor nodes. Our waveform set approach allows us to utilize a global glitch filtering technique that can model the removal ofglitches in more detail. It produces error free estimates for tree structured circuits. For other circuit, experimental results using the ISCAS'85 benchmarks show that the waveform set method generally provides significantly better estimates of the transition density compared to previous techniques.

As the latest process technologies are combined with steadily increasing design sizes, the result is a dramatic increase in the number of scan test vectors that must be applied during manufacturing test. This in turn may result in costly tester reloads and unacceptable test application times. In this paper the authors present a finite memory test response compactor (a class of compactors originally proposed in Rajski et al., 2003) which is diagnosis friendly. The latter is important to maintain throughput on the test floor (Stanojevic et. al., 2005, Leininger et. al., 2002). Yet, the compactor has comparable performance to other schemes Rajski et al., 2003, Mitra et al., 2004, Mitra et al., 2004) when it comes to `X' tolerance and aliasing

This paper describes the design of a remote fault simulator for delay faults that can be used by students to investigate the effect of different stimuli generators for different types of delay fault models.

A novel storage requirement estimation methodology is presented for use in the early system design phases when the data transfer ordering is only partially fixed. At that stage, none of the existing estimation tools are adequate, as they either assume a fully specified execution order or ignore it completely. A prototype CAD tool has been developed that includes major parts of the storage requirement estimation and optimization methodology. Using representative application demonstrators, we show how our techniques and tool can effectively guide the designer to achieve a transformed specification with low storage requirement.

A novel storage requirement estimation methodology is presented for use in the early system design phases when the data transfer ordering is only partly fixed. At that stage, none of the existing estimation tools are adequate, as they either assume a fully specified execution order or ignore it completely. This paper presents an algorithm for automated estimation of strict upper and lower bounds on the individual data dependency sizes in high-level application code given a partially fixed execution ordering. In the overall estimation technique, this is followed by a detection of the maximally combined size of simultaneously alive dependencies, resulting in the overall storage requirement of the application. Using representative application demonstrators, we show how our techniques can effectively guide the designer to achieve a transformed specification with low storage requirement.

In this paper, we propose a novel storage requirement estimation methodology for use in the early system design phases when the data transfer ordering is only partially fixed. At that stage, none of the existing estimation tools are adequate, as they either assume a fully specified execution order or ignore it completely. Using representative application demonstrators, we show how our technique can effectively guide the designer to achieve a transformed specification with low storage requirement.

This paper presents and implementation of a novel microprocessor architecture for executing byte compiled Java programs directly in hardware. The processor features two programming models, a Java model and a RISC model. The entities share a common data path and may operate independently although not in parallel. This combination facilities access to hardware-near instructions and provides powerful interrupt and instruction trapping capabilities. Our processor targets medium to small embedded applications where performance in the sense of throughput is not the primary design objective, but rather the ability to execute Java code on a processor core with small die size and acceptable power consumption characteristics.

For data dominated applications, the system level design trajectory should first focus on finding a good data transfer and storage solution. Since no realization details are available at this level, estimates are needed to guide the designer. This paper presents an algorithm for automated estimation of strict upper and lower bounds on the individual data dependency sizes in high level application code given a partially fixed execution ordering. Previous work has either not taken execution ordering into account at all, resulting in large overestimates, or required a fully specified ordering which is usually not available at this high level. The usefulness of the methodology is illustrated on representative application demonstrators.

A new DCT architecture developed by Mou and Jutand (1991) is compared to an architecture based on distributed arithmetic with ROMs realized as random logic. Both architectures have been implemented in 0.8 /spl mu/m CMOS technology and optimized with different constraints on area and timing. The results reveal that for HDTV applications the design with distributed arithmetic is superior, with lower power consumption and less than half the chip area.

The authors consider the analysis of the state transition graph (STG) as a key to understanding the state and fault coverage of BIST (built-in self-test) schemes. Some interesting topological properties of STGs are found. These may be exploited when BIST schemes are being designed. Specifically, the problem of limit cycles in STGs is discussed, and ways of defining initial states to yield long paths before state repetition are presented. One BIST scheme that has modest overhead requirements and is based on serial shift registers is given. The scheme is applied to some of the ISCAS-89 benchmark circuits, and experimental results on fault coverage are presented.>