Branch prediction is important in high-performance processors and its importance continues to grow. In the drive for higher execution frequencies, pipelines are lengthened and memory latencies are increased. This increases the cost of branch mispredictions. In this paper we describe some behavior patterns of branches. We believe that understanding the behavior of branches is helpful when designing fetch mechanisms for high-performance microprocessors. We also examine several current branch predictors and discuss how they work. Finally, we look at some of the challenges that we are faced with when designing fetch mechanisms and predictors for future microprocessors and discuss some of the possible solutions.

There is wide agreement that one of the most important impediments to the performance of current and future pipelined superscalar processors is the presence of conditional branches in the instruction stream. Speculative execution seems to be one solution of choice to the branch problem, but speculative work is discarded if a branch is mispredicted. Therefore, we need a very accurate branch predictor; 95% accuracy is not good enough. This paper proposes branch classification to help improve the accuracy of branch predictors. Branch classification allows an individual branch instruction to be associated with the branch predictor best suited to predict its direction. Using this approach, a hybrid branch predictor can be constructed such that each component branch predictor predicts those branches for which it is best suited. This paper suggests one classification scheme, analyzes several branch predictors, and proposes a hybrid branch predictor that achieves higher prediction accuracy than any branch predictor previously reported in the literature.

High performance computer implementation today is increasingly directed toward parallelism in the hard-

Recent attention to speculative execution as a mecha-nism for increasing performance of single instruction streams has demanded substantially better branch prediction than what has been previously available. We [1, 2] and Pan, So, and Rahmeh [4] have both proposed variations of the same aggressive dynamic branch pre-dictor for handling those needs. We call the basic model Two-Level Adaptive Branch Prediction; Pan, So, and Rahmeh call it Correlation Branch Prediction. In this paper, we adopt the terminology of [2] and show that there are really nine variations of the same basic model. We compare the nine variations with respect to the amount of history information kept. We study the effects of different branch history lengths and pattern history table configurations. Finally, we evaluate the cost effectiveness of the nine variations. 1

Presents a comparison of superscalar and decoupled access/execute architectures. Both architectures attempt to exploit instruction-level parallelism by issuing multiple instructions per cycle, employing dynamic scheduling to maximize performance. Simulation results are presented for four different configurations, demonstrating that the architectural queues of the decoupled machines provide similar functionality to register renaming, dynamic loop unrolling, and out-of-order execution of the superscalar machines with significantly less complexity.>

As the issue rate and depth of pipelining of high performance Superscalar processors increase, the importance of an excellent branch predictor becomes more vital to delivering the potential performance of a wide-issue, deep pipelined microarchitecture. We propose a new dynamic branch predictor (Two-Level Adaptive Branch Prediction) that achieves substantially higher accuracy than any other scheme reported in the literature. The mechanism uses two levels of branch history information to make predictions, the history of the last k branches encountered, and the branch behavior for the last s occurrences of the specific pattern of these k branches. We have identified three variations of the Two-Level Adaptive Branch Prediction, depending on how finely we resolve the history information gathered. We compute the hardware costs of implementing each of the three variations, and use these costs in evaluating their relative effectiveness. We measure the branch prediction accuracy of the three variations of two-Level Adaptive Branch Prediction, along with several other popular proposed dynamic and static prediction schemes, on the SPEC benchmarks. We show that the average prediction accuracy for Two-Level Adaptive Branch Prediction is 97 percent, while the other known schemes achieve at most 94.4 percent average prediction accuracy. We measure the effectiveness of different prediction algorithms and different amounts of history and pattern information. We measure the costs of each variation to obtain the same prediction accuracy.

Article Single instruction stream parallelism is greater than two Share on Authors: Michael Butler Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MichiganView Profile , Tse-Yu Yeh Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MichiganView Profile , Yale Patt Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MichiganView Profile , Mitch Alsup Motorola Incorporated, Microprocessor and Memory Technology Group, 6501 William Cannon Drive West, Austin, Texas Motorola Incorporated, Microprocessor and Memory Technology Group, 6501 William Cannon Drive West, Austin, TexasView Profile , Hunter Scales Motorola Incorporated, Microprocessor and Memory Technology Group, 6501 William Cannon Drive West, Austin, Texas Motorola Incorporated, Microprocessor and Memory Technology Group, 6501 William Cannon Drive West, Austin, TexasView Profile , Michael Shebanow Motorola Incorporated, Microprocessor and Memory Technology Group, 6501 William Cannon Drive West, Austin, Texas Motorola Incorporated, Microprocessor and Memory Technology Group, 6501 William Cannon Drive West, Austin, TexasView Profile Authors Info & Claims ISCA '91: Proceedings of the 18th annual international symposium on Computer architectureApril 1991 Pages 276–286https://doi.org/10.1145/115952.115980Online:01 April 1991Publication History 98citation1,234DownloadsMetricsTotal Citations98Total Downloads1,234Last 12 Months81Last 6 weeks43 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Article Free Access Share on Two-level adaptive training branch prediction Authors: Tse-Yu Yeh Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MichiganView Profile , Yale N. Patt Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MichiganView Profile Authors Info & Claims MICRO 24: Proceedings of the 24th annual international symposium on MicroarchitectureSeptember 1991 Pages 51–61https://doi.org/10.1145/123465.123475Online:01 September 1991Publication History 483citation5,042DownloadsMetricsTotal Citations483Total Downloads5,042Last 12 Months372Last 6 weeks42 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF