ABSTRACT Agriculture is a backbone of the Indian economy and people's lives. In agriculture land, soil is the most important element on which the quality of production and efficiency depends to the maximum extent. Phosphorus (P), Nitrogen (N), Potassium (K), and the potential of hydrogen (pH) are the key nutrients in soil. An efficient crop recommender and prediction system is needed to optimize agriculture practices considering the escalating demand for more food. Traditional time‐consuming and manual farming should be replaced with a smart agriculture framework using the integration of technologies like the Internet of Things (IoT), Wireless Sensor Network (WSN), and Machine Learning (ML). This paper proposed an IoT‐WSN driven crop management system with Neuro‐ML Ensemble Model, utilizing LoRaWAN Gateway, that can be deployed in the agriculture field to collect real‐time soil parameters. In this paper for soil nutrient analysis, the author used various ML algorithms such as Naive Bayes (NB), Logistic Regression (LR), K‐Nearest Neighbor (KNN), Decision Tree (DT), Random Forest (RF), Ada Boost (AB), Gradient Boosting (GB), and Support Vector Machine (SVM) and recommending a suitable ML algorithm for the crop recommender system. For crop yield prediction, the author has developed and recommended a customized GB Algorithm with an accuracy of 98.80%, and for the fertilizer recommendation system, the author has suggested CNN‐BiGRU which outperforms other approaches like BiGRU and CNN with an average accuracy rate of 92.48%. The author presented work with respect to the Indian agriculture sector and compared ML algorithms with state‐of‐the‐art datasets available on some government websites of India, and used by other authors, with a dataset collected by the author from hardware using Raspberry Pi. For crop recommendation and forecasting, the Neuro‐ML Ensemble model employs the Neuro‐ML, which combines neural networks (NN) with the ML models. This research aspires to assist farmers in opting for suitable crops as per their environmental suitability and situation by analyzing and predicting which crops suit well to fit the parameters required to enhance crop growth like soil nutrients, soil moisture, soil pH, and rainfall, etc. The author obtained accuracy for various ML models used in the framework. For NB, LR, KNN, SVM, DT, and RF, the author obtained accuracies of 99.54%, 96.36%, 95.90%, 96.81%, 98.86%, and 99.31%, respectively, using the Kaggle dataset available as open access. Through a dataset collected by the authors, we obtained accuracies of 94.54%, 91.36%, 92.72%, 92.73%, 86.36%, and 94.54% for NB, LR, KNN, SVM, DT, and RF, respectively. The author found that Naive Bayes (NB) outperforms the other machine learning algorithms, such as KNN, SVM, LR, Decision Tree, RF, and AB, and is the best algorithm suited for crop yield.

Video sharing (e.g., YouTube, Vimeo, Facebook, TikTok) accounts for the majority of internet traffic, and video processing is also foundational to several other key workloads (video conferencing, virtual/augmented reality, cloud gaming, video in Internet-of-Things devices, etc.). The importance of these workloads motivates larger video processing infrastructures and – with the slowing of Moore’s law – specialized hardware accelerators to deliver more computing at higher efficiencies. This paper describes the design and deployment, at scale, of a new accelerator targeted at warehouse-scale video transcoding. We present our hardware design including a new accelerator building block – the video coding unit (VCU) – and discuss key design trade-offs for balanced systems at data center scale and co-designing accelerators with large-scale distributed software systems. We evaluate these accelerators “in the wild" serving live data center jobs, demonstrating 20-33x improved efficiency over our prior well-tuned non-accelerated baseline. Our design also enables effective adaptation to changing bottlenecks and improved failure management, and new workload capabilities not otherwise possible with prior systems. To the best of our knowledge, this is the first work to discuss video acceleration at scale in large warehouse-scale environments.

Intrinsically disordered regions/proteins (IDRs) are abundant across all the domains of life, where they perform important regulatory roles and supplement the biological functions of structured proteins/regions (SRs). Despite the multifunctionality features of IDRs, several interrogations on the evolution of viral genomic regions encoding IDRs in diverse viral proteins remain unreciprocated. To fill this gap, we benchmarked the findings of two most widely used and reliable intrinsic disorder prediction algorithms (IUPred2A and ESpritz) to a dataset of 6108 reference viral proteomes to unravel the multifaceted evolutionary forces that shape the codon usage in the viral genomic regions encoding for IDRs and SRs. We found persuasive evidence that the natural selection predominantly governs the evolution of codon usage in regions encoding IDRs by most of the viruses. In addition, we confirm not only that codon usage in regions encoding IDRs is less optimized for the protein synthesis machinery (transfer RNAs pool) of their host than for those encoding SRs, but also that the selective constraints imposed by codon bias sustain this reduced optimization in IDRs. Our analysis also establishes that IDRs in viruses are likely to tolerate more translational errors than SRs. All these findings hold true, irrespective of the disorder prediction algorithms used to classify IDRs. In conclusion, our study offers a novel perspective on the evolution of viral IDRs and the evolutionary adaptability to multiple taxonomically divergent hosts.

In this paper, we present a purpose-built data management system, MLdp, for all machine learning (ML) datasets. ML applications pose some unique requirements different from common conventional data processing applications, including but not limited to: data lineage and provenance tracking, rich data semantics and formats, integration with diverse ML frameworks and access patterns, trial-and-error driven data exploration and evolution, rapid experimentation, reproducibility of the model training, strict compliance and privacy regulations, etc. Current ML systems/services, often named MLaaS, to-date focus on the ML algorithms, and offer no integrated data management system. Instead, they require users to bring their own data and to manage their own data on either blob storage or on file systems. The burdens of data management tasks, such as versioning and access control, fall onto the users, and not all compliance features, such as terms of use, privacy measures, and auditing, are available. MLdp offers a minimalist and flexible data model for all varieties of data, strong version management to guarantee re-producibility of ML experiments, and integration with major ML frameworks. MLdp also maintains the data provenance to help users track lineage and dependencies among data versions and models in their ML pipelines. In addition to table-stake features, such as security, availability and scalability, MLdp's internal design choices are strongly influenced by the goal to support rapid ML experiment iterations, which cycle through data discovery, data exploration, feature engineering, model training, model evaluation, and back to data discovery. The contributions of this paper are: 1) to recognize the needs and to call out the requirements of an ML data platform, 2) to share our experiences in building MLdp by adopting existing database technologies to the new problem as well as by devising new solutions, and 3) to call for actions from our communities on future challenges.

IEEE Std P1838 is the DfT standard-under-development for 3D test access into dies meant to be used in 3D multi-die stack assemblies. P1838 is the first DfT standard to include a flexible parallel port (FPP): an optional, scalable multi-bit ('parallel') test access mechanism, offering higher test access bandwidth compared to the mandatory one-bit ('serial') port. In this paper, we describe P1838's FPP and propose a formal FPP specification language based on Google's Protocol Buffers (PBs), that potentially could become part of the standard. For a realistic example FPP, we provide its formal specification. Finally, we report on a demonstrator software tool, developed by using PBs-generated data access routines, that converts an FPP specification into a corresponding Verilog netlist.

DFT Compression and limiting power during test are two of the recent active areas of interest in the domain of DFT and Manufacturing Test. Many of the low-power test techniques, as well as DFT compression schemes exploit the `don't-care' bits in ATPG vectors to achieve the desirable results, and hence often can be in conflict with each other. In this paper, we show how we can alter a commonly known DFT compression scheme - Illinois-Scan-Chain design, also known as Broadcast-Scan, for low power test. Results show the effectiveness of the proposed DFT Compression scheme in reducing switching power during test.

This paper describes a simple means to enable direct diagnosis by bypassing MISRs on a small set of tests while achieving ultimate output compression using MISRs for the majority of tests. By combining two compression schemes, XOR and MISRs in the same device, it becomes possible to have high compression and still support volume diagnostics.

This paper describes a structured test re-use methodology and infrastructure for core-based system chips. The methodology is based on the use of a structured test bus framework that provides access to virtual components in a system chip allowing the test methodologies and test vectors for these components to be re-used. It addresses the test access, isolation, interconnect and shadow logic test problems without requiring modifications to the components, even for cores with more ports than chip pins. The test area overhead required, including test bus routing, to implement this methodology can be less than 1%.

This paper describes the first behavioral synthesis system that incorporates a hierarchical test generation approach to synthesize area-efficient and highly testable controller/data path circuits. Functional information of circuit modules is used during the synthesis process to facilitate complete and easy testability of the data path. The controller behavior is taken into account while targeting data path testability. No direct controllability of the controller outputs through scan or otherwise is assumed. The test set for the combined controller/data path is generated during synthesis in a very short time. Near 100% testability of combined controller and data path is achieved. The synthesis system easily handles large bit-width data path circuits with sequential loops and conditional branches in their behavioral specification, and scheduling constructs like multicycling, chaining and structural pipelining. An improvement of about three to four orders of magnitude was usually obtained in the test generation time for the synthesized benchmarks as compared to an efficient gate-level sequential test generator. The testability overheads are almost zero. Furthermore, in many cases at-speed testing is also possible.

In this paper test compaction techniques suitable for circuits designed using a novel parallel access scan methodology are proposed. In this methodology, groups of scan elements are addressed in parallel and the scan-in and scan-out operations are performed separately. The compaction techniques presented reduce the number of scan-in/out operations required by skipping scan operations that do not have an affect on fault coverage. The techniques allow the number of test cycles required to be reduced by up to 45% of that achieved using regular dynamic compaction techniques alone, and by up to 98% over that achieved using a single serial scan chain methodology. In addition, the techniques are suitable for both synchronous and asynchronous circuits.

A novel direct access test methodology that unifies the testing of pre-designed intellectual property blocks and custom user designed logic is proposed. This methodology allows the test logic and wiring used for testing custom logic to be shared for testing intellectual property using pre-computed test vectors. It provides parallel access to storage elements and so alleviates some of the issues found in serial access scan techniques. It also provides a novel solution to the non-scan element state retention problem found in single edge-triggered clock based serial scan approaches.

In this paper, we present methods for synthesis of sequential circuits for easy testability based on a scheme previously referred to as synthesis for parallel scan. A heuristic is used to achieve maximal merging of the testability logic with the normal combinational logic of the sequential circuit in order to minimize the area overhead. The latches used in the proposed scheme are normal nonscan latches. The synthesis for parallel scan scheme is applied to two different fault models. To facilitate stuck-at-fault testability of sequential circuits, the synthesis for parallel scan method is augmented with a novel structural analysis technique for selection of latches for partial scan with emphasis on minimization of delay overhead. Experimental results on ISCAS '89 benchmarks resynthesized by our method indicate that one can, in general, achieve the same level of testability with less area and delay overheads, as compared to the conventional structural analysis method for partial scan. A method for synthesizing fully hazard-free robust path-delay fault testable sequential circuits using the concept of synthesis for parallel scan is also presented. When the number of primary inputs of the sequential circuit is at least as large as the number of latches, only normal nonscan latches are required. Experimental results on MCNC and ISCAS '89 benchmarks show the area overheads to be very reasonable. No previous method could ensure complete robust testability of all path-delay faults in a sequential circuit without assuming a completely enhanced scan, even under the above condition. However, when this condition is not met, i.e., the number of primary inputs is less than the number of latches, we introduce the concept of synthesis for maximally parallel enhanced scan. This still provides complete robust testability, however, at the expense of a higher area overhead.

Most existing behavioral synthesis systems put emphasis on optimizing area and performance. Only recently has some research been done to consider testability during behavioral synthesis. In our previous work, we integrated hierarchical testability with behavioral synthesis of simple digital data path circuits to synthesize highly testable circuits (S. Bhatia and N.K. Jha, 1994). In the current work, we consider the testability of complete controller and data path during behavioral synthesis. The methods presented can easily handle large and complex behavioral descriptions with loops, conditionals, and allow different scheduling constructs, such as pipelining, multicycling, and chaining. The test set for the combined controller/data path is generated during synthesis in a very short time and near 100% fault coverage is obtained for almost all the synthesized circuits at practically zero overheads.>

Testing of sequential circuits is greatly facilitated by using scan techniques to directly control and observe the latches. Adding scan capability after logic synthesis may incur significant area and delay overheads. For such cases, we present a technique called synthesis for parallel partial scan in which latches are incrementally selected for partial scan based on some new structural analysis criteria that we introduce. Delay overhead is minimized, in most cases made zero or nearly zero, by judiciously selecting the latches in the non-critical paths. A heuristic is used to maximally merge the scan logic with the combinational logic of the sequential circuit to minimize the area overhead. The latches used in our scheme are normal, non-scan latches. Experimental results on ISCAS '89 benchmarks resynthesized by our method indicate that we can, in general, achieve the same level of testability with fewer latches selected for partial scan, as compared to previous methods based on structural analysis.>