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Masayuki Ikeda

dblp:57/4503 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
High-performance computing · 56% Processor architecture and microarchitecture · 28% Interconnection networks and networks-on-chip · 8%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing
supercomputer architecture		 0.011994
Architecture of the VPP500 parallel supercomputer · SC 1994
Processor architecture and microarchitecture
vector processor		 0.011994
Architecture of the VPP500 parallel supercomputer · SC 1994
High-performance computing › supercomputer architecture
vector supercomputer		 0.011994
Architecture of the VPP500 parallel supercomputer · SC 1994
Interconnection networks and networks-on-chip › switch architecture
crossbar switch		 0.011994
Architecture of the VPP500 parallel supercomputer · SC 1994
Distributed systems › distributed system architecture
distributed multiprocessor system		 0.011994
Architecture of the VPP500 parallel supercomputer · SC 1994
YearPublicationVenuePosition
1994 Architecture of the VPP500 parallel supercomputer
abstract
The VPP500 vector parallel processor is a highly parallel, distributed memory supercomputer that has a performance range of 6.4 to 355 gigaFLOPS and a main memory capacity from 1 to 222 gigabytes. The system scalably supports between 4 and 222 processors interconnected by a high-bandwidth crossbar network. Three key aspects of the VPP500, which are in sharp contrast to current massively parallel systems, characterize its architecture. First the building block is a 1.6 gigaFLOPS vector processor that is more than an order of magnitude faster than the processors used in massively parallel processors (MPP). This high uniprocessor performance reduces the dependence on parallelism. Second the distributed memory architecture and high-bandwidth crossbar network eliminate many of the bottlenecks found in MPP systems. These allow efficient utilization of hardware and have the effect of lessening the complexity of programming parallel computers. Third the system realizes high throughput by its capability to arbitrarily partition the processing elements for flexible multiprocessing.>
Teruo Utsumi, Masayuki Ikeda, Moriyuki Takamura
 SC2