This paper presents an overview of the physical layer (PHY) and medium access control layer (MAC) requirements for a new class of high-speed wireless local area networks (WLANs) operating in the 5 GHz Unlicensed National Information Infrastructure (UNII) bands at data rates of 6-54 Mbps.

This paper presents the architecture, design and implementation of a 16 point FFT processor for a high speed wireless local area network. The 110000-transistor chip is implemented in 0.6 /spl mu/m TLM CMOS, operates worst case at 50 MHz at a supply voltage of 2.5 volts, and consumes 80 mW.

This paper summarizes aspects of the VLSI development of a high-speed wireless local area network (WLAN). The implications for system-on-a-chip designs are summarized.

We have implemented the digital section of a wireless local area network (WLAN) demodulator in a reconfigurable interface card called the PCI Pamette. The entire baseband section of the demodulator has been implemented using the Pamette and a simple analog to digital mezzanine board. This is the second version of the demodulator, the first being a card-based design using a mixture of discrete and reconfigurable logic. The Pamette design took far less time to complete than the card-based one. Moreover, the reconfigurable substrate is much more versatile. We describe the Pamette implementation and discuss our experiences with the two different design styles and technologies.

HIPERLAN is a high speed wireless LAN standard adopted by the ETSI. It operates in 150 MHz of spectrum in the 5 GHz band, with up to five TDD channels provided for duplex data transmission at up to 23.5 Mb/s. This paper shows that in the presence of cochannel cells and full link utilisation, HIPERLAN performs poorly when using its DCA-type clear channel assessment (CCA) scheme, and that the target performance levels are only achievable under optimal FCA-type channel assignments. Two main factors contribute to this poor performance: HIPERLAN has insufficient channels to meet C/I constraints in the presence of cochannel cells; and the CCA scheme results in poor channel distributions.

: An interference model developed for arbitrary microcellular networks, based upon a parameter called the `Interference to Noise Ratio' or INR, is used to derive interference and cell radius statistics for mobile stations in a microcellular network. The theoretical INR and cell radius statistics for simple interference environments show good agreement with numerical Monte Carlo simulations. For more complex environments, it is hypothesised that the Central Limit Theorem could be applied to approximate the behaviour of an interferer ensemble, enabling the cell radius statistics for a network to be expressed in terms of the system design parameters. Simulations of microcell ensembles that support this hypothesis are presented. I. INTRODUCTION Microcellular technologies are being developed with a view to satisfy the vision of a personal communicator in every pocket. The aims of a future Personal Communications Service (PCS) provided by a ubiquitous microcell network include [1]: # Low...

Described is an alternative simple description of FET drain current that provides the flexibility of an extra parameter which can be chosen to approximate the Shockley expression or general power law. An empirical polynomial expression which uses only integer powers is used to provide computational efficiency. The expression gives the designer a more accurate FET model which is consistent for both large- and small-signal simulations.>

Article Free Access Share on PIAF: a knowledge-based/algorithm top-down floorplanning system Authors: M. A. Jabri Systems Engineering and Design Automation Laboratory, Sydney Univewity Electrical Engineering, NSW 2006 Australia Systems Engineering and Design Automation Laboratory, Sydney Univewity Electrical Engineering, NSW 2006 AustraliaView Profile , D. J. Skellern Systems Engineering and Design Automation Laboratory, Sydney Univewity Electrical Engineering, NSW 2006 Australia Systems Engineering and Design Automation Laboratory, Sydney Univewity Electrical Engineering, NSW 2006 AustraliaView Profile Authors Info & Claims DAC '89: Proceedings of the 26th ACM/IEEE Design Automation ConferenceJune 1989 Pages 582–585https://doi.org/10.1145/74382.74480Published:01 June 1989Publication History 6citation157DownloadsMetricsTotal Citations6Total Downloads157Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF