In high-end microprocessors, control-logic timing can gate the cycle time, but control logic is specified late and changes often. Custom design is too time consuming for control implementation, and application specific integrated circuit (ASIC)-like methods have difficulty achieving the required performance/area targets. In this paper, we describe C5M, a new layout system for high-performance control logic which has been successfully used in the design of a recent 400 MHz IBM processor. Results from this design are used to show that C5M achieves near custom quality with high productivity and predictability.

In high-end microprocessors, control-logic timing can gate the cycle time, but control is specified late and changes often.Custom design is too time-consuming for control implementation, yet ASIC-like methods have difficulty achieving the performance/area targets.In this paper we describe GM, a new layout system for control logic, which has been successfully used in the design of a recent 400 MHz IBM processor.Results from this design are used to show that C5M achieves near-custom quality with high productivity.

Three multirow layout problems are presented: transistor orientation, contact positioning and symbolic-to-shape translation. It is shown that these multirow problems have a common property, called quantitative dependency. Using this property, an optimization technique which is based on a penalty-delay strategy is presented. It is proved that the penalty-delay strategy assures optimality, and that the optimal solution can be obtained in linear time. The algorithmic approach is based on the observation that optimal layout decisions in any region within a cell or a macro depend only on quantitative measures of the decisions in other regions, rather than on their details. This suggests a departure from the traditional approach of handling the different regions separately and combining them afterward into a single unit, an approach that may degrade the quality of the final layout. Instead, the entire macro can be processed at once, taking into account the mutual quantitative dependency between distinguished regions.>

An algorithmic framework is presented for mapping CMOS circuit diagrams into area-efficient, high-performance layouts in the style of one-dimensional transistor arrays. Using efficient search techniques and accurate evaluation methods, the huge solution space that is typical to such problems is transversed extremely fast, yielding designs of hand-layout quality. In addition to generating circuits that meet prespecified layout constraints in the context of a fixed target image, on-the-fly optimizations are performed to meet secondary optimization criteria. A practical dynamic programming routing algorithm is utilized to accommodate the special conditions that arise in this context. This algorithm has been implemented and is currently used at IBM for cell-library generation.>

We describe an algorithm that maps a CMOS circuit diagram into an area-efficient, high-performance layout in the style of a transistor chain. It is superior to other published algorithms of this kind in terms of the class of input circuits it accepts, its efficiency, and the quality of the results it produces. This algorithm is intended for the automatic generation of basic cells in a custom or semicustom design environment, thereby removing the burden of arduous mask definition from the designer. We show how our method was used to compose cells in a row into a functional slice (e.g. an adder) that can be used in, say, a data path.