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Larry M. Augustin

dblp:57/4936 · DBLP profile ↗
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6ranked-venue papers
3as first author
0since 2021 · last 2002
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 4 · 1 first-authorSystems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
2 papers
Empirical software engineering · 75% Requirements engineering and software design · 25%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 72% Distributed systems · 28%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Empirical software engineering
collaborative software development
0.012002
Accelerating software development through collaboration · ICSE 2002
Empirical software engineering › open source software
open source software development
0.012002
Accelerating software development through collaboration · ICSE 2002
Requirements engineering and software design › software architecture › architecture description
architecture description language
0.011995
Specification and Analysis of System Architecture Using Rapide · IEEE Trans. Software Eng. 1995
Requirements engineering and software design
software architecture
0.011995
Specification and Analysis of System Architecture Using Rapide · IEEE Trans. Software Eng. 1995
Empirical software engineering
software engineering practice
0.012002
Accelerating software development through collaboration · ICSE 2002
Electronic design automation › hardware verification and test
formal verification
0.011988
Verification of VHDL Designs Using VAL · DAC 1988
Electronic design automation
hardware verification and test
0.011988
Verification of VHDL Designs Using VAL · DAC 1988
Distributed systems › distributed database
distributed transactions
0.011995
Specification and Analysis of System Architecture Using Rapide · IEEE Trans. Software Eng. 1995

Methods — techniques the papers use, named apart from their topics

poset execution model · 0.0event-based modeling · 0.0VAL · 0.0
YearPublicationVenuePosition
2002 Accelerating software development through collaboration
abstract
In early 1999, VA Software launched a project to understand how the Internet development community had been able to produce software such as Linux, Apache and Samba that was generally developed faster and with higher quality than comparable commercially available alternatives [1,2,3,20]. Our goal was simple: determine how to make more software development projects successful.We discovered that successful Internet community projects employed a number of practices that were not well characterized by traditional software engineering methodologies. We now refer to those practices as Collaborative Software Development or CSD. Late in 1999 we developed the SourceForge platform to make it easy for even small software development projects to employ those practices, and in November of 1999 launched the SourceForge.net web site based on the SourceForge platform.The site was an overwhelming success, and in less than two years, grew to support more than 27,000 software development projects and over a quarter million software developers worldwide. SourceForge.net affords us an unequaled test bed for understanding CSD. In response to demand from companies seeking to enable CSD within their organizations, we announced a commercial version of the SourceForge platform, SourceForge Enterprise Edition, in August 2001.This paper describes the principles of CSD, the software development pain points those principles address, and our experience enabling CSD with the SourceForge platform.
Larry M. Augustin, Dan Bressler, Guy Smith
ICSE1
1995 Specification and Analysis of System Architecture Using Rapide
abstract
Rapide is an event-based, concurrent, object-oriented language specifically designed for prototyping system architectures. Two principle design goals are: (1) to provide constructs for defining executable prototypes of architectures and (2) to adopt an execution model in which the concurrency, synchronization, dataflow, and timing properties of a prototype are explicitly represented. This paper describes the partially ordered event set (poset) execution model and outlines with examples some of the event-based features for defining communication architectures and relationships between architectures. Various features of Rapide are illustrated by excerpts from a prototype of the X/Open distributed transaction processing reference architecture.>
David C. Luckham, John J. Kenney, Larry M. Augustin, James Vera, Doug Bryan, Walter Mann
IEEE Trans. Software Eng.3
1995 Correction to "Specification and Analysis of System Architecture Using Rapide"
David C. Luckham, John J. Kenney, Larry M. Augustin, James Vera, Doug Bryan, Walter Mann
IEEE Trans. Software Eng.3
1993 Partial orderings of event sets and their application to prototyping concurrent, timed systems
abstract
RAPIDE is a concurrent, object-oriented language specifically designed for prototyping large concurrent systems. One of the principle design goals has been to adopt a computation model in which the synchronization, concurrency, data flow, and timing aspects of a prototype are explicitly represented and easily accessible both to the prototype itself and to the prototyper. This article describes the partially ordered event set (poset) computation model and the features of RAPIDE for using posets in reactive prototypes and for automatically checking posets. An example prototyping scenario illustrates uses of the poset computation model, with and without timing.
David C. Luckham, James Vera, Doug Bryan, Larry M. Augustin, Frank C. Belz
J. Syst. Softw.4
1989 Timing models in VAL/VHDL
abstract
A detailed description is given of the timing model of VHDL (VHSIC hardware description language). VHDL uses a two-level timing model based on discrete event simulation. Timed assignment statements are preemptive, and two forms of preemption are supported in the language: inertial and transport. The author describes the VAL (VHDL annotation language) timing model and features of VAL designed to work with the VHDL timing model. VAL introduces assertions that understand the two-level timing framework in VHDL. In contrast to the preemptive assignment of VHDL, VAL models the same behavior using only anticipatory semantics (no preemption). The anticipatory model enables VAL descriptions to be treated as constraints on the input/output behavior of a device that may be directly translated into predicates. The author demonstrates by a simple example the application of formal techniques for manipulating these predicates.>
Larry M. Augustin
ICCAD1
1988 Verification of VHDL Designs Using VAL
Larry M. Augustin, Benoit A. Gennart, Youm Huh, David C. Luckham, Alec G. Stanculescu
DAC1