Due to their scalability and energy efficiency, memristor-based analog neuromorphic chips (MANCs) have significant advantages in edge computing. Researchers use software to train network parameters, then in hardware deployment, weights are translated into memristor conductances and biases are provided by digital-to-analog converters (DACs). Analog operational amplifiers are utilized for neural signal summation. Nowadays, efficient design, training, and implementation of MANCs have not been thoroughly explored. Particularly, MANC co-design considering software training and hardware deployment has not been studied. To address this issue, we propose Constraints-Aware Training (CAT), which includes hardware constraints of memristor devices, operational amplifiers, and DACs in the training process, thereby enabling co-design between offline training and hardware deployment. To evaluate the proposed methodology, a 4-layer fully connected network (FC-4) and a convolutional network (LeNet-5) are trained by CAT on MNIST and CIFAR-10 datasets, and then deployed in hardware circuits. Experimental results demonstrate that incorporating hardware constraints during offline training through CAT enables convenient and successful MANC hardware solutions.

Since sparse neural networks usually contain many zero weights, these unnecessary network connections can potentially be eliminated without degrading network performance. Therefore, well-designed sparse neural networks have the potential to significantly reduce the number of floating-point operations (FLOPs) and computational resources. In this work, we propose a new automatic pruning method-sparse connectivity learning (SCL). Specifically, a weight is reparameterized as an elementwise multiplication of a trainable weight variable and a binary mask. Thus, network connectivity is fully described by the binary mask, which is modulated by a unit step function. We theoretically prove the fundamental principle of using a straight-through estimator (STE) for network pruning. This principle is that the proxy gradients of STE should be positive, ensuring that mask variables converge at their minima. After finding Leaky ReLU, Softplus, and identity STEs can satisfy this principle, we propose to adopt identity STE in SCL for discrete mask relaxation. We find that mask gradients of different features are very unbalanced; hence, we propose to normalize mask gradients of each feature to optimize mask variable training. In order to automatically train sparse masks, we include the total number of network connections as a regularization term in our objective function. As SCL does not require pruning criteria or hyperparameters defined by designers for network layers, the network is explored in a larger hypothesis space to achieve optimized sparse connectivity for the best performance. SCL overcomes the limitations of existing automatic pruning methods. Experimental results demonstrate that SCL can automatically learn and select important network connections for various baseline network structures. Deep learning models trained by SCL outperform the state-of-the-art human-designed and automatic pruning methods in sparsity, accuracy, and FLOPs reduction.

Singular value decomposition (SVD) is one of the most effective algorithms in recommender systems (RSs). Due to the iterative nature of SVD algorithms, one big challenge is initialization that has a major impact on the convergence and performance of RSs. Unfortunately, existing SVD algorithms in the literature typically initialize the user and item features in a random manner; thus, data information is not fully utilized. This work addresses the challenge of developing an efficient initialization method for SVD algorithms. We propose a general neural embedding initialization framework, where a low-complexity probabilistic autoencoder neural network initializes the features of user and item. This framework supports explicit and implicit feedback data sets. The design details of our proposed framework are elaborated and discussed. Experimental results show that RSs based on our proposed initialization framework outperform the state-of-the-art methods in rating prediction. Moreover, regarding item ranking, our proposed framework shows an improvement of at least 2.20% ~5.74% than existing SVD algorithms and other matrix factorization methods in the literature.

This paper proposes two pico-ampere voltage references (VRs) for Internet-of-Things (IoT). The first VR is composed of two subthreshold PMOS transistors. It achieves a minimum temperature coefficient (TC) of 29 ppm/°C, a current consumption of 50.5 pA, a line regulation of 7,206 ppm/V, and a power supply rejection ratio (PSRR) of -28 dB at 100 Hz. In order to satisfy the better line regulation and PSRR requirement of high-end IoT systems, a five-PMOS VR is proposed to realize ultra-high performance in the line regulation and PSRR. By employing a regulation technique, the impacts of drain-induced barrier lowering (DIBL), gate-inducted drain leakage (GIDL), and gate-drain capacitance feedthrough are largely mitigated. Therefore, high performance in line regulation and PSRR are obtained. The post-layout simulation results based on a 0.18 μm standard CMOS process show that the proposed five-PMOS VR achieves a line regulation of 23.6 ppm/V over a supply voltage from 1.0 V to 2.0 V. Besides, the simulated PSRR is -62 dB@100Hz when the total current consumption is 101 pA at 27°C.

This paper presents a highly parallel hardware architecture for rate estimation in a High Efficiency Video Coding intra encoder to increase the level of parallelism and reduce the computational time. The adopted rate estimation algorithm is fully compatible with the context-adaptive binary arithmetic coding (CABAC) bit rate estimation except ignoring a syntax element “split_cu_flag.” Design considerations, analysis, and circuit implementation are elaborated. This design has been verified with the HM-15.0 reference software. It achieves an average decrease of 0.005% and an average increase of 0.0092 dB in Bjøntegaard delta (BD)-rate and BD-peak signal-to-noise ratio, respectively. This proposed hardware architecture is implemented in Verilog and synthesized in FPGAs and ASICs. It supports resolutions up to 3840 × 2160 at 30 f/s. Compared with stateof-the-art hardware designs for rate estimation in the literature, the proposed architecture achieves substantial performance improvement in rate estimation accuracy and reliability, with the overhead of a relatively larger chip area and higher power consumption. To the best of our knowledge, this is the first highly parallel hardware architecture of table-based CABAC bit rate estimator, which is attractive in time-constrained and highperformance video coding applications.

High computational complexity and heavy data/timing dependency in high efficiency video coding (HEVC) hinder the throughput of video encoding. In order to address both design challenges, we present high-performance algorithm adaptations and high-throughput hardware architecture for the HEVC intra encoders. Particularly, the chroma intra prediction includes the derived luma mode, which greatly improves the worst-case video compression performance. Compared with the HM-15.0 reference software, the proposed algorithms reduce the computational workload by 22%, while the average BD-Rate and BD-PSNR for classes A-F and 4K are 2.79% and -0.13 dB, respectively. This BD-Rate is lower than existing designs in the literature with the same video resolution. The field-programmable gate array (FPGA) implementation of proposed design shows it operates at 120 MHz and supports 45 f/s of 1080P video sequences using 196K logic elements and 127-KB on-chip SRAM. The application-specified integrated circuit (ASIC) implementation of the proposed design in TSMC 90 nm technology shows that its clock frequency reaches 320 MHz with a hardware gate count of 2186K and power consumption of 290 mW, and it supports real-time encoding of 4K videos at 30 f/s.

The growing demand for high-performance ultra-high-definition video coding leads to H.265/high-efficiency video coding (HEVC), where the increased computational complexity and data/timing dependence hinder its coding throughput. To address these challenges, this paper presents four algorithm adaptations and a fully parallel hardware architecture for an H.265/HEVC intra encoder. To the best of our knowledge, this is the first fully parallel H.265/HEVC intra encoder. This design supports 35 prediction modes and all coding tree unit partitions. All PUs are independently processed in four prediction engines for high parallelism. An appropriate set of intra prediction modes, RDO candidates, and CABAC rate estimate instances is assigned to each prediction engine, where internal computational tasks are pipelined and scheduled to maximize the processing throughput. Compared with the HM-15.0 software, the proposed algorithm adaptations lead to a reduction of 27% in computational workload, while the average BD-rate and BD-PSNR are 4.39% and -0.21 dB, respectively. This BD-rate is lower than the existing designs with the same video resolution. FPGA implementation of the proposed design shows that it operates at 120 MHz and supports 45 fps of 1080P video sequences using 201-K logic elements and 120-KB on-chip SRAM. ASIC implementation of the proposed design in TSMC 90-nm technology shows that its clock frequency reaches 320 MHz with a hardware gate count of 2288 K, and that it supports real-time encoding of 30 fps of 4-K video sequences. Compared with the state-of-the-art designs, our proposed design demonstrates advantages in computational complexity, bit rate, video quality, throughput, reliability, and flexibility.

Variable block size motion estimation has contributed greatly to achieving an optimal interframe encoding, but involves high computational complexity and huge memory access, which is the most critical bottleneck in ultra-high-definition video encoding. This article presents a hardware-efficient block matching algorithm with an efficient hardware design that is able to reduce the computational complexity of motion estimation while providing a sustained and steady coding performance for high-quality video encoding. A three-level memory organization is proposed to reduce memory bandwidth requirement while supporting a predictive common search window. By applying multiple search strategies and early termination, the proposed design provides 1.8 to 3.7 times higher hardware efficiency than other works. Furthermore, on-chip memory has been reduced by 96.5% and off-chip bandwidth requirement has been reduced by 39.4% thanks to the proposed three-level memory organization. The corresponding power consumption is only 198mW at the highest working frequency of 500MHz. The proposed design is attractive for high-quality video encoding in real-time applications with low power consumption.

This paper presents a 5.8 GHz dedicated short range communication (DSRC) CMOS RF-SoC transceiver with digitally controlled RF architecture for China electronic toll collection (ETC) system. The operation of key RF blocks, such as ASK modulator, power amplifier, LNA, and mixer, are directly controlled by digital baseband. Compared with state-of-the-art designs in literature, this work demonstrates remarkable advantages in design simplicity, Tx output peak power, adjacent channel power ratio (ACPR), dynamic range, occupied bandwidth (OBW), bit error rate (BER), and so on.

In a multithreaded execution environment, race condition leads to computational errors and system hazards. Up to date, a series of task scheduling strategies have been presented in the literature to reduce the risk of race condition. Because of the increasing complexity of this problem in multi-core systems, existing task scheduling approaches are not very efficient. To deal with this challenge, in this work, we develop a race-condition-aware and hardware-oriented task partitioning and scheduling algorithm using entropy maximization model. We model uncertainty as a probabilistic occurrence within a time interval, and hence the characteristics of event ordering are analyzed through an uncertainty matrix. Next, a metric is developed to measure the uncertainty of task execution in various execution environments. Finally, a maximum entropy model is generated to ensure the lowest probability of race condition during task execution. The smallest one among maximum entropy values is chosen and used in our proposed task scheduling algorithm. Experimental results show that the proposed task scheduling strategy based on our maximum entropy model outperforms existing state-of-the-art approaches. For example, in a 128-core computing system, the task execution time, CPU utilization ratio, and throughput of our proposed task scheduling is improved by$15.3\sim 36.4$percent,$8.2\sim 17.6$percent, and$20.7\sim 41.4$percent, respectively. Moreover, our proposed scheduling algorithm exhibits low computational complexity and good adaptivity to diverse execution environments.

This paper presents modeling, design, and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems. The proposed design methodology is suitable for energy harvesting systems employed in low-cost applications, such as wireless sensor networks. Our approach is unique in achieving maximum output power by cross-layer optimization of poly-silicon solar cells (thickness, grain boundaries and cell configuration) and power converter circuits. Simulation results indicate that optimizing the solar cell along with the power converter improves the system output power by 16% compared to a baseline approach of optimizing the two components separately.

In low temperature polycrystalline silicon (LTPS) based display technologies, the electrical parameter variations in thin film transistors (TFTs) caused by random grain boundaries (GBs) result in significant yield loss, thereby impeding its wide deployment. In this paper, from a system and circuit design perspective, we propose a new self-repair design methodology to compensate the GB-induced variations for LTPS liquid crystal displays (LCDs) and active-matrix organic light emitting diode (AMOLED) displays. The key idea is to extend the charging time for detected low drivability pixel switches, hence, suppressing the brightness non-uniformity and eliminating the need for large voltage margins. The proposed circuit was implemented in VGA LCD panels which were used for prediction of power consumption and yield. Based on the simulation results, the proposed circuit decreases the required supply voltage by 20% without performance and yield degradation. 7% yield enhancement is observed for high resolution, large sized LCDs while incurring negligible power penalty. This technique enables LTPS-based displays either to further scale down the device size for higher integration and lower power consumption or to have superior yield in large sized panels with small power overhead.

Micro-scale energy harvesting has become an increasingly viable and promising option for powering ultra-low power systems. A power converter is a key component in micro-scale energy harvesting systems. Various design parameters of the power converter, most notably the number of stages in a multi-stage power converter, play a crucial role in determining the amount of electrical power that can be extracted from a micro-scale energy transducer such as a miniature solar cell. Existing stage number optimization techniques for switched capacitor power converters, when used for energy harvesting systems, result in a substantial degradation in the amount of harvested electrical power. To address this problem, this paper proposes a new stage number optimization technique for switched capacitor power converters that maximizes the net harvested power in micro-scale energy harvesting systems. The proposed technique is based on a new figure-of-merit that is well suited for energy-harvesting systems. We have validated the proposed technique through circuit simulations using IBM 65nm technology. Our simulation results demonstrate that the proposed stage number optimization technique results in an increase of 60%-290% in net harvested power, compared to existing stage number optimization techniques.

In this work, we present a vibration-based energy scavenging system based on piezoelectric conversion for micropower applications. A novel maximum power point (MPP) tracking scheme is proposed to harvest the maximum power from the vibration system. A time-multiplexing mechanism is employed to perform energy harvesting and MPP tracking alternately. In the MPP tracking mode, a voltage reference that represents the optimal output voltage at the MPP is generated. A control unit then uses this reference to track the system operation around the MPP. The proposed system is capable of self-starting up without the help of an energy buffer. As a result, it is suitable for battery-less applications or when the energy buffer is completely drained. This tracking scheme has very small power overhead and is simple to implement in VLSI. Hence, it is especially applicable for micropower systems. The entire design was fabricated in a 0.35-μ m CMOS process. Experimental results verified the proposed MPP tracking scheme and demonstrated the system operation. Measurement results show that the power harvesting efficiency of the electrical circuitry is higher than 90%.

Harvesting electrical power from environmental energy sources is an attractive and increasingly feasible option for several micro-scale electronic systems such as biomedical implants and wireless sensor nodes that need to operate autonomously for long periods of time (months to years). However, designing highly efficient micro-scale energy harvesting systems requires an in-depth understanding of various design considerations and tradeoffs. This paper provides an overview of the area of micro-scale energy harvesting and discusses the various challenges and considerations involved from a system-design perspective.

Energy harvesting has emerged as a feasible and attractive option to improve battery lifetime in micro-scale electronic systems such as biomedical implants and wireless sensor nodes. A key challenge in designing micro-scale energy harvesting systems is that miniature energy transducers (e.g., photovoltaic cells, thermo-electric generators, and fuel cells) output very low voltages (0-0.4V). Therefore, a fully on-chip power converter (usually based on a charge pump) is used to boost the output voltage of the energy transducer and transfer charge into an energy buffer for storage. However, the charge transfer capability of widely used linear charge pump based power converters degrades when used with ultra-low voltage energy transducers. This paper presents the design of a new tree topology charge pump that has a reduced charge sharing time, leading to an improved charge transfer capability. The proposed design has been implemented using 65nm technology and circuit simulations demonstrate that the proposed design results in an increase of up to 30% in harvested power compared to existing linear charge pumps.

Maximum power point (MPP) tracking is a technique to maximize the amount of power harvested from energy transducers such as solar cells. MPP tracking presents new design challenges when used in the context of micro-scale energy harvesting systems, where the area dedicated to solar cells is small (in the range of sub or a few cm2) and hence, the power output is in the range of a few mW. This paper provides an overview of several low-overhead MPP tracking approaches that are attractive for micro-scale solar energy harvesting. These include: design-time component matching method, fractional open-circuit voltage or fractional short-circuit current method, and variants of the generic hill-climbing approach. We also illustrate using a simple case study, how MPP from a full-system perspective may differ from the MPP of the photovoltaic module itself in micro-scale harvesting systems.

Thermal energy harvesting using micro-scale thermoelectric generators is a promising approach to alleviate the power supply challenge in ultra low power systems. In thermal energy harvesting systems, energy is extracted from the transducer using an interface circuitry, which plays a key role in the determining the energy extraction efficiency. This paper presents techniques for the systematic modeling, analysis, and design of interface circuitry used in micro-scale thermoelectric energy harvesting systems. We characterize the electrical behavior of a micro-scale thermoelectric transducer connected to a step-up charge pump based power converter and model the relationship between the transducer output voltage and the charge pump switching frequency. We model various power loss components inside the interface circuitry and present an analytical design methodology that estimates optimal parameter values for the interface circuitry. These parameter values lead to maximum net output power being delivered to the energy buffer. We have implemented various interface circuitries using IBM 65nm technology to verify our proposed models and methodology. Circuit simulation results show that the proposed methodology accurately estimates the maximum power point voltage of the system with an error of 3%.

This paper proposed a vibration driven energy harvesting platform based on piezoelectric material. A new maximum power point tracking (MPPT) method for this platform is also presented. This platform harvests ambient vibration energy as its power source, and is capable of self-starting, and self-powered operation without the need of a battery. The proposed MPPT methodology consumes very little power, and is especially suitable for the environments, where ambient harvested power is very low. System modeling, analysis, and implementation are developed. Simulation results show that the power harvesting efficiency with the proposed MPPT scheme is higher than 90% and the power utilization efficiency of the overall platform is higher than 50%.

In this work, the design of a mechanical vibration energy scavenging and management system is presented for ultra low power applications. A new maximum power point tracking (MPPT) scheme is proposed for piezoelectric conversion. This scheme consumes very little power and is especially suitable for ultra low power energy harvesting applications. This design is capable of self-starting and self-powered, thus eliminates external battery integration and significantly reduces the system volume. System modeling, analysis, and VLSI implementation were developed. Various simulations were carried out and the simulation results show that the proposed MPPT scheme can achieve an energy harvesting efficiency higher than 90%.