We discuss the design and implementation of VISAGE, an object-oriented user interface framework that is part of GE's FACE Flexible Architecture Compiler Environment [1]. High-level services include a domain-independent graph editor that provides standard methods for viewing and editing hierarchical graphs, including graph layout. Editors that are customized to a specific application are built by inheritance of the domain-independent graph editor's functionality and overloading of the display, selection and editing methods. At a lower layer, presentation objects are responsible for parsing user input, displaying application output, providing mouse sensitivity and command dialogue execution. These presentation objects separate the application from its user interface, and thus promote system modularity.

Many aspects of design automation software have similar requirements for representing, manipulating, and storing design information. The recognition of these common requirements in CAD tools, allows the Flexible Architecture Compilation Environment's (FACE) Core Environment to provide a suite of high level tools for the CAD developer. The Core Environment software has been developed using object-oriented software technology, and may be readily adapted to specific applications. The focus of the core environment is to improve the productivity of CAD tool developers through better tool integration and a state-of-the-art software development environment. This Core Environment software has been used in the development of an integrated tool set covering algorithm specification, structural synthesis, and physical assembly of digital hardware systems. The focus of this paper is on the Core Environment's organization and its use in application tool development.

The Flexible Architecture Compilation Environment (FACE) provides a common object-oriented representation for design information. A module-generation system built within the FACE environment that uses parameterized procedural module descriptions is discussed. These generators capture the knowledge of a designer and facilitate a high level of reuse of the modules and leaf cells. The system provides a general mechanism to parameterize design information and supports complex generators ranging from tiled structures to entire chips. This approach is applicable to many hardware architectures. Experience in the design of working VLSI chips is discussed.>

After a brief discussion of previous work in the field of behavioral-to-structural translation, the bit-serial architecture which is the target of the bit-serial compiler is discussed. The bit-serial language (BSL) is then defined, and the details of the behavioral-to-structural translation are given.>

This paper describes a fully integrated silicon compilation tool geared towards digital signal processing applications. The silicon compiler presented here uses a bit-serial architecture with a 1.25- µm CMOS cell library. It accepts as its input a high-level description language tailored for digital signal processing algorithms. The language supports the basic signal processing constructs such as multiplication, addition, subtraction, sample delays, logical operators, relational operators, as well as a conditional assignment. The compiler is equipped with behavioral, logic, and fault simulators, and performs placement and routing. The paper also details the use of the silicon compiler for the implementation of classical DSP algorithms: digital filters, FFT, programmable filters, as well as other more specialized applications such as adaptive algorithms and waveform synthesis. Moreover, some techniques are presented to implement more complex mathematical functions commonly used in DSP. The results of chip designs using the compiler and its impact on future designs are highlighted.