Demo Data from EDBT 2026 / reviewers in the wild / expert
Janet Wu
dblp:57/6308
· DBLP profile ↗
4ranked-venue papers
2as first author
0since 2021 · last 2007
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
High-performance computing · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization › parallelizing compiler
distributed memory compilation |
0.0 | 1 | 1995 | Distributed Memory Compiler Design for Sparse Problems · IEEE Trans. Computers 1995 |
Compilers and program optimization
parallelizing compiler |
0.0 | 1 | 1995 | Distributed Memory Compiler Design for Sparse Problems · IEEE Trans. Computers 1995 |
High-performance computing
distributed memory systems |
0.0 | 1 | 1995 | Distributed Memory Compiler Design for Sparse Problems · IEEE Trans. Computers 1995 |
Methods — techniques the papers use, named apart from their topics
runtime support library · 0.0message passing · 0.0loop nest compilation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2007 | Testing of Vega2, a chip multi-processor with spare processorsabstractVega2 is a CMP (chip multi-processor) with 48 processor cores, and several spare cores to improve yield. The chip also contains about 1000 memory macros both inside and outside the processor cores. The larger memories have column redundancy as well. The main DFT challenge for Vega2 is to produce an architecture that makes it easy to identify defective processors, thoroughly test the memories and efficiently apply ATPG patterns. Samy Makar, Tony Altinis, Niteen Patkar, Janet Wu |
ITC | 4 |
| 1995 | Distributed Memory Compiler Design for Sparse ProblemsabstractThis paper addresses the issue of compiling concurrent loop nests in the presence of complicated array references and irregularly distributed arrays. Arrays accessed within loops may contain accesses that make it impossible to precisely determine the reference pattern at compile time. This paper proposes a run time support mechanism that is used effectively by a compiler to generate efficient code in these situations. The compiler accepts as input a Fortran 77 program enhanced with specifications for distributing data, and outputs a message passing program that runs on the nodes of a distributed memory machine. The runtime support for the compiler consists of a library of primitives designed to support irregular patterns of distributed array accesses and irregularly distributed array partitions. A variety of performance results on the Intel iPSC/860 are presented.> Janet Wu, Raja Das, Joel H. Saltz, Harry Berryman, Seema Hiranandani |
IEEE Trans. Computers | 1 |
| 1991 | Runtime Compilation Methods for Multicomputers
Janet Wu, Joel H. Saltz, Seema Hiranandani, Harry Berryman |
ICPP (2) | 1 |
| 1991 | Multiprocessors and run-time compilationabstractAbstract Run‐time preprocessing plays a major role in many efficient algorithms in computer science, as well as playing an important role in exploiting multiprocessor architectures. We give examples that elucidate the importance of run‐time preprocessing and show how these optimizations can be integrated into compilers. To support our arguments, we describe transformations implemented in prototype multiprocessor compilers and present benchmarks from the iPSC2/860, the CM‐2 and the Encore Multimax/320. Joel H. Saltz, Harry Berryman, Janet Wu |
Concurr. Pract. Exp. | 3 |