This paper introduces a new concurrent processing model called Communicating Logic (CL). As the target architecture we adopt the dual layered Plastic Cell Architecture (PCA). Data-path-oriented processing functionality is encapsulated in asynchronous hardware objects with variable graining and implemented using look-up tables. Communication (i.e. connectivity and control) between the distributed processing objects is achieved by means of inter-object message passing. The key point of the CL approach is that it offers the merits of scalable, high performance hardware implementation with the compilation and linking capabilities unique to software.

This paper proposes a new processor architecture for manipulating protocols in digital signal transport systems. To realize flexible and high-performance digital signal transport systems, the architecture has unique application-specific hardware with a core CPU. It is derived from an analysis of functions in real systems. A computer simulation confirms the efficiency of the architecture.

This paper presents a new technique for improving the performance of a synchronous circuit configured as a look-up table based FPGA without changing the initial circuit configuration; only the register location is altered. It improves clock speed and data throughput at the expense of latency. One of the most significant benefits realized by this approach is that the time-consuming and user-uncontrollable reconfiguration processes, i.e., remapping, replacement, and rerouting, are unnecessary when improving circuit performance. After applying our technique to some benchmark circuits, the average performance improvement was 33% for six combinational circuits, and 25% for 18 sequential circuits.>

This paper discusses a new architecture for programmable hardware targeted at high-speed digital telecommunication systems and describes a preliminary design. The basic architecture of the programmable hardware is proposed based on the characteristics of functions and an analysis of logic used in actual communication subsystems performing high-speed bit level operations. The proposed architecture, called PROTEUS, includes a pipeline structure of logic and latch groups, and a 2-stage logic block structure that consists of small LUTs and wide gates. The design strategy of a prototype chip and the CAD techniques used to achieve the required performance are also discussed.>

A multicomputer-type parallel processing system has been developed that offers a peak performance of 12.8 GFLOPS. This system is called NOVI-II HiPIPE, and was designed for super-high-definition (SHD) image processing. SHD image is a new image medium and its resolution is higher than that of HDTV. Because SHD image processing requires computing power that exceeds the ability of any single digital signal processor (DSP), current or anticipated, NOVI-II HiPIPE uses a multicomputer-type parallel processing architecture. A 100-MFLOPS vector processor serves as the backend processor of each processing element. The current version of NOVI-II HiPIPE uses 128 mesh connected processing elements and 128 vector processors. The configuration and performance of NOVI-II HiPIPE are described.>

The VLSI design of a one-chip vector processor (VP) for parallel digital signal processing (DSP) systems is described. The VP aims at a peak performance of 100 MFLOPS (32-b) for typical digital signal processing applications. To achieve this performance based on existing CMOS technology, a very-long-instruction-word-type pipeline architecture was used. The pipeline processing architecture and the functional units configuration are shown. A high-level behavioral-description-based CAD system called PARTHENON was used to design the functions and logic circuits of VP. The suitability and effectiveness of PARTHENON for the VP design are shown in terms of parallel operation and pipeline-stage description. The estimated work load in the VP design with PARTHENON is one order of magnitude smaller compared to conventional CAD tools.>

A new speech coding and multiplexing scheme matched to the asynchronous transfer mode is described. A block coding technique that is based on a variable-rate coding algorithm that makes the most of the burstiness of voice information is employed. The main feature of the scheme is considerable bit reduction, which is attained by a fairly simple algorithm. It is demonstrated that the proposed algorithm exhibits better quality than that of a 32 kb/s ADPCM at a mean bit rate of less than 13 kb/s. The effect of statistical multiplexing is verified by means of simulation employing long conversational speech samples. Methods for constructing variable- and fixed-length frames (units of information multiplexed and transferred in the network) are proposed. The proposed coding algorithm is shown to be applicable to both variable- and fixed-length frame strategies.>

An exploration is made of some techniques which will play important roles in the development of the future universal transport network. In the network, the information can be efficiently integrated and transported by making the most of the burstiness of the information flows and of the store-and-forward process at the transport nodes. First, a coding and multiplexing scheme for audio signals matched to the above transportation mode is proposed. The effectiveness of the scheme is demonstrated through computer simulation and the extent of the deviations are provided for some sets of parameters. The analysis provides useful tools to perform sensitivity analysis of network delay performance.>