The practical application of aerial-aquatic robots is hindered by severe impact loads during water entry. Existing load reduction methods are inefficient for robots requiring rapid, high-frequency aerial-aquatic transitions. Therefore, this study proposes an active learning based joint optimization framework for nose profiles and water-entry strategies, which is fully automated. Specifically, an 8-dimensional parameter space is defined for generating dataset inputs through Latin Hypercube Sampling (LHS). Furthermore, a Deep Kernel Learning (DKL) surrogate model is trained under different water-entry strategies, in order to predict peak impact loads and quantify prediction uncertainty for varying nose profiles. Within each active learning loop, the Non-dominated Sorting Genetic Algorithm III (NSGA-III) guides the selective labelling of samples to expand the dataset, and the DKL model is iteratively retrained until convergence. Compared against state-of-the-art methods, the proposed approach reduces the number of required high-fidelity Computational Fluid Dynamics (CFD) simulations to 65% of that of the comparison methods, while achieving maximum reductions of 66.9% in axial and 72.8% in normal impact loads across the parameter space, respectively. Notably, under the water-entry strategies employed by the hunting behavior of gannets, the approach yields profiles closely matching the skull morphology of the northern gannet. In this case, this work not only delivers an efficient and reliable impact loads reduction solution for aerial-aquatic robots, but also reveals the role of natural selection in minimizing such loads.

We investigate the problem of decoupling capacitance (decap) allocation for power supply noise suppression at floorplan level. First, we assume that a floorplan is given and consider the decap placement as a postfloorplan step. Second, we consider the decap placement as an integral part of a floorplanning methodology (noise-aware floorplanning). In both cases, the objective is to minimize the floorplan area while suppressing the power supply noise below the specified limit. Experimental results on MCNC benchmark circuits show that, for postfloorplan decap placement, the white space allocated for decap is about 6%-9% of the chip area for the 0.25-/spl mu/m technology. The power-supply noise is kept below the specified limit. Compared to postfloorplan approach, the peak power-supply noise can be reduced by as much as 40% and the decap budget can be reduced by as much as 21% by using noise-aware floorplanning methodology. The total area is also reduced due to the reduced total decap budget gained from reduced power supply noise.

We investigate the problem of decoupling capacitance allocation for power supply noise suppression at floorplan level. Decoupling capacitance budgets for the circuit modules are calculated based on the power supply noise estimates. A linear programming technique is used to maximize the allocation of the existing white space in the floorplan for the placement of decoupling capacitors. An incremental heuristic is proposed to insert more white space into the existing floorplan to meet the remaining demand required for decoupling capacitance fabrication. Experimental results on six MCNC benchmark circuits show that the white space allocated for decoupling capacitance is about 6%-12% of the chip area for the 0.25μμ technology, and the power supply noise can be kept below 10%Vdd.

In this paper, we propose an approach for the analysis of power supply noise in the frequency domain for power/ground (P/G) networks of tree topologies. We model the P/G network as a linear time invariant (LTI) pseudo-distributed RLC network and the gates (or cells) as time-varying current sources. Voltage fluctuation caused by the switching events is calculated based on the effective impedances seen by the corresponding current sources and the spatial correlation between the nodes of the power network. Superposition is applied to the LTI system to obtain the overall noise spectrum at any node of the power supply network. Inverse Fast Fourier Transformation (IFFT) is then performed on the frequency domain noise spectrum to obtain the time domain noise waveform. The proposed algorithm has a complexity of O(n/sup 2/). Experimental results show that our approach can produce accurate noise waveforms.

In this paper, we propose an event-driven simulation based approach to estimate the worst case IR drop and Ldi/dt inductive noise an the power supply network. The switching noise is modeled as a weighted sum of the switching currents and the rates of change of the switching currents, where the weights are respectively the effective resistance and inductance (on the P/G network) experienced by each switching current. Monte Carlo and genetic algorithm are employed to search for the worst case input vector pair(s) that induce the maximum switching noise. The worst case input patterns are used in the SPICE simulation to verify the switching noise waveforms on the power supply network. Experimental results show that the worst case switching noise on the power supply network for ISCAS85 benchmark circuits implemented in TSMC 0.25 /spl mu/m technology can be as high as 40% of the supply voltage V/sub dd/.