The ever-increasing propensity for intellectual property (IP) reuse has reduced the design productivity gap in the supply chain. As a consequence, protecting IPs has become more difficult since IP vendors now make their IPs more flexible so that they can be reused in other designs for greater profits. This has made IP piracy and infringement easier than ever. IP watermarking can detect IP piracy and infringement and it has been an active research topic for the past decade. Various watermarking techniques have been discussed in the literature that embed circuitry into IP to provide proof of ownership. But, in most RT-level watermarking methods, the watermarking circuit is separate from IP functionality and can be easily identified and tampered with. In this paper, we propose CAPEC, a Cellular Automata (CA) guided watermarking technique that embeds watermarking circuits into the don’t care states of the FSM. The watermarking function is a set of configurable CA rules tightly coupled with the functional states of the FSM. CAPEC generates a signature in a challenge-response-based protocol, is resistant to identification, tampering, and removal attacks, and has minimal overhead. We also analyze and evaluate the efficiency of the technique and its resilience to different attacks for varying challenge size and CA rules. After watermarking different benchmarks, the watermark overhead was found to be negligible and formal verification proved no changes to the functional circuit.

The pursuit of manufacturing cost reduction reshaped the conventional system-on-chip (SoC) design and manufacturing flow into the horizontal business model. In this model, the design house loses control of the design during the manufacturing process. Therefore, this shift has introduced potential vulnerabilities at each stage of the flow and provides adversaries ample opportunities to cause piracy, security, and trust concerns. Further, SoCs deployed in IoT, smart, and mission-critical devices contain sensitive assets to perform security-critical applications, requiring an on-chip security engine (SE) to ensure protecting assets and secure operation throughout the lifecycle. In this paper, we present an end-to-end secure SoC lifecycle management flow that establishes trust at each stage of the manufacturing process, prevents potential security threats, provides secure provisioning schemes, and protects the chip from in-field and supply chain vulnerabilities.

IEEE Std P1838 is the DfT standard-under-development for 3D test access into dies meant to be used in 3D multi-die stack assemblies. P1838 is the first DfT standard to include a flexible parallel port (FPP): an optional, scalable multi-bit ('parallel') test access mechanism, offering higher test access bandwidth compared to the mandatory one-bit ('serial') port. In this paper, we describe P1838's FPP and propose a formal FPP specification language based on Google's Protocol Buffers (PBs), that potentially could become part of the standard. For a realistic example FPP, we provide its formal specification. Finally, we report on a demonstrator software tool, developed by using PBs-generated data access routines, that converts an FPP specification into a corresponding Verilog netlist.

The IEEE Standard 1149.4 has been ratified and available for some time, now. However, describing the architectural content of an analog boundary-scan register has not yet been standardized. The work of the IEEE Std 1149.4 Working Group over the past several years has been to define and codify an extension to IEEE Std 1149.1 's BSDL. In this paper, a language to describe the boundary-scan implementation in a mixed-signal device is proposed. The language is called analog boundary-scan description language (ABSDL) and it is compatible with the existing IEEE Std 1149.1 BSDL. Using this language, test generation automation can proceed, and interconnect test on a mixed-signal board using analog boundary-scan cells can be performed to test both simple wires and discrete components between packaged devices with IEEE Std 1149.1 and 1149.4 infrastructure and access. Although not yet promulgated, the syntax definitions proposed in this paper are indicative of the current state of the Working Group's attempts at this effort. Along with the generation of the syntax for describing IEEE Std 1149.4 structures, the semantic checks for such an ABSDL file are presented

Single board, and now multi-board testability is highly conditioned by the availability of various forms of boundary scan technology. This paper surveys the three more recent IEEE Standards relating to boundary scan. The paper is based on three backgrounders prepared by members of the individual Working Groups for the IEEE Standards booth at ITC 2003.

The IEEE P1149.4 Mixed-Signal Test Bus Working Group is on the cusp of delivering a document that will finally standardize the architecture for, and the method of access to, the analog portion of mixed-signal circuits for test and diagnostic applications. This Standard will have the same profound effect on the design and test community that IEEE 1149.1 had previously. P1149.4 gives the test infrastructure the capability to measure discrete impedances external to devices supporting the Standard using a 6-wire bus. This bus uses 4 of the same signals used today to support 1149.1 compliant devices and subsystems. This paper will detail the basic architecture; give some design-specific information and data learned through the Standard's development process; relate results from several test devices; and provide a basic example of usage.