Newest manufacturing technologies with feature sizes smaller than 20nm and FinFET devices have favored more restrictive design rules for manufacturability while suffering from electrical limitations of electromigration (EM) and variability. Designers can no longer reap the benefits in power, performance and area by simply relying on feature size miniature with contemporary design techniques. This work illustrates the importance of design and manufacturing technology co-optimization. Limitations in lithography has led to slower reduction in metal and VIA shape spacing than critical dimensions, which prompts for co-optimization in metallization stack, power mesh planning, standard cell designs and placement algorithms. New routing algorithms and parasitics modeling are required to achieve improved design performance under sky-rocketing metal resistance especially at lower metal levels. Ever-lowering maximum current limits due to EM has prompted new approaches in placement optimization to counteract the potential explosion in EM violations. Adoption of FinFET has allowed ultra-low Vdd designs, which requires careful consideration of Vth offerings that allow proper trade-off between variability, area and power efficiency.

A wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical methodologies for faster turnaround time. In this paper, we propose a novel routability-driven analytical placement algorithm for hierarchical mixed-size circuit designs. This paper presents a novel design hierarchy identification technique to effectively identify design hierarchies and guide placement for better wirelength and routability. The proposed algorithm optimizes routability from four major aspects: 1) narrow channel handling; 2) pin density; 3) routing overflow optimization; and 4) net congestion optimization. Routability-driven legalization and detailed placement are also proposed to further optimize routing congestion. Compared with the participating teams for the 2012 ICCAD Design Hierarchy Aware Routability-driven Placement Contest, our placer can achieve the best quality (both the average overflow and wirelength) and the best overall score (by additionally considering running time).

A wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical methodologies for faster turnaround time. This paper presents a novel two-stage technique to effectively identify design hierarchies and guide placement for better wirelength and routability. To optimize wirelength and routability simultaneously during placement, a new analytical net-congestion-optimization technique is also proposed. Compared with the participating teams for the 2012 ICCAD Design Hierarchy Aware Routability-driven Placement Contest, our placer can achieve the best quality (both the average overflow and wire-length) and the best overall score (by additionally considering running time).

Through-silicon vias (TSVs) are required for transmitting signals among different dies for the 3-D integrated circuit (IC) technology. The significant silicon areas occupied by TSVs bring critical challenges for 3-D IC placement. Unlike most published 3-D placement works that only minimize the number of TSVs during placement due to the limitations in their techniques, this paper proposes a new 3-D cell placement algorithm that can additionally consider the sizes of TSVs and the physical positions for TSV insertion during placement. The algorithm consists of three stages: 1) 3-D analytical global placement with density optimization and whitespace reservation for TSVs; 2) TSV insertion and TSV-aware legalization; and 3) layer-by-layer detailed placement. In particular, the global placement is based on a novel weighted-average (WA) wirelength model, giving the first published model that can outperform the well-known log-sum-exp wirelength model theoretically and empirically. Also, a scheme is proposed to enhance the numerical stability of the WA wirelength model. Furthermore, 3-D routing can easily be accomplished by traditional 2-D routers since the physical positions of TSVs are determined during placement. Experimental results show the effectiveness of our algorithm. Compared with state-of-the-art 3-D cell placement works, our algorithm can achieve the best routed wirelength, TSV counts, and total silicon area, in shortest running time.

Datapath is one of the most important components in high performance circuit designs, such as microprocessors, as it is used to manipulate all data. For better performance, a datapath is usually placed with high regularity and compactness. Although cell placement has been studied extensively, not much work addresses the optimization of datapaths which are often treated as big macros. In this paper, we propose a structure-aware placement algorithm that can exploit the regular structures of datapath circuits and meanwhile leverage effective techniques to achieve high quality and scalability. Our algorithm applies a nonlinear optimization for wirelength minimization and a sigmoid based density model for density control in datapath circuits. Compared with state-of-the-art works, our algorithm can achieve the best structure-aware placement results efficiently.

A modern chip often contains large numbers of predesigned macros (e.g., embedded memories, IP blocks) and standard cells, with very different sizes. The fast-growing design complexity with large-scale mixed-size macros and standard cells has caused significant challenges to modern circuit placement. Analytical algorithms have been shown to be most effective for standard-cell placement, but the problems with the rotation and legalization of large macros impose intrinsic limitations for analytical placement. Consequently, most recent works on mixed-size placement resort to combinatorial macro placement. Instead, this paper presents the first attempt to resolve the intrinsic problems with a unified analytical approach. Unlike traditional analytical placement that uses only wire and density forces to optimize the positions of circuit components, we present a new force, the rotation force, to handle macro orientation for analytical mixed-size placement. The rotation force tries to rotate each macro to its desired orientation based on the wire connections on this macro. A cross potential model is also proposed to increase the rotation freedom during placement. The final orientation of each macro with legalization consideration is then determined by mathematical programming. A macro flipping force is also proposed to determine the flipping orientation of each macro at the end of global placement. Compared with start-of-the-art mixed-size placement approaches (such as FLOP, CG, and MP-tree), our approach achieves the best average wirelength efficiently.

Through-silicon vias (TSVs) are required for transmitting signals among different dies for the three-dimensional integrated circuit (3D IC) technology. The significant silicon areas occupied by TSVs bring critical challenges for 3D IC placement. Unlike most published 3D placement works that only minimize the number of TSVs during placement due to the limitations in their techniques, this paper proposes a new 3D cell placement algorithm which can additionally consider the sizes of TSVs and the physical positions for TSV insertion during placement. The algorithm consists of three stages: (1) 3D analytical global placement with density optimization and whitespace reservation for TSVs, (2) TSV insertion and TSV-aware legalization, and (3) layer-by-layer detailed placement. In particular, the global placement is based on a novel weighted-average wirelength model, giving the first model in the literature that can outperform the well-known log-sum-exp wirelength model theoretically and empirically. Further, 3D routing can easily be accomplished by traditional 2D routers since the physical positions of TSVs are determined during placement. Compared with state-of-the-art 3D cell placement works, our algorithm can achieve the best routed wirelength, TSV counts, and total silicon area, in shortest running time.

Due to the significant mismatch between existing wirelength models and the congestion objective in placement, considering routability during placement is particularly significant for modern circuit designs. In this paper, a novel routability-driven analytical placement algorithm for large-scale mixed-size circuit designs is proposed. Unlike most existing works which usually optimize routability by reallocating whitespace or net-based congestion removal, the proposed algorithm optimizes routability from three major aspects: (1) Pin density: Most existing works optimize routability based on net distribution, while our work considers both the density of pins and their routing directions; (2) Routing overflow optimization: Unlike most previous works that use white space allocation or net-based congestion removal to improve routability, our work optimizes routing overflow by a novel sigmoid function during global placement; (3) Macro porosity consideration: A virtual macro expansion technique is applied to consider the constrained routing resource incurred by big macros. Routability-driven legalization and detailed placement are also proposed to further optimize routing congestion. Experimental results show the effectiveness and efficiency of our proposed algorithm. Compared with the participating teams for the 2011 ACM ISPD Routability-Driven Placement Contest, our algorithm achieves the best average overflow and routed wirelength.

A modern chip often contains large numbers of pre-designed macros (e.g., embedded memories, IP blocks) and standard cells, with very different sizes. The fast-growing design complexity with large-scale mixed-size macros and standard cells has caused significant challenges to modern circuit placement. Analytical algorithms have been shown to be most effective for standard-cell placement, but the problems with the rotation and legalization of large macros impose intrinsic limitations for analytical placement. Consequently, most recent works on mixed-size placement resort to combinatorial macro placement. Instead, this paper presents the first attempt to resolve the intrinsic problems with a unified analytical approach. Unlike traditional analytical placement that uses only wire and density forces to optimize the positions of circuit components, we present a new force, the rotation force, to handle macro orientation for analytical mixed-size placement. The rotation force tries to rotate each macro to its desired orientation based on the wire connections on this macro. A cross potential model is also proposed to increase the rotation freedom during placement. The final orientation of each macro with legalization consideration is then determined by mathematical programming at the end of global placement. Experimental results show the effectiveness and efficiency of our approach. Compared with state-of-the-art mixed-size placement approaches (such as FLOP, CG, and MP-tree), our approach achieves the best average wirelength efficiently.

Post-silicon validation has recently drawn designers' attention due to its increasing impacts on the VLSI design cycle and cost. One key feature of the post-silicon validation is the use of spare cells. In the literature, most existing works focus on developing new delicate spare cell structures. On the other hand, the placement of spare cells has a crucial impact on the design cycle and cost of the post-silicon debugging; however, there exists not much work on this placement problem. In this paper, we propose the first spare-cell-aware analytical placement framework which predicts the spare cell requirement and considers spare cell insertion during global placement. We also propose a multilevel spare cell insertion technique which provides a more efficient spare cell planning and a better control of quality impact due to spare cell insertion. To guide the selection of available spare cell positions during insertion, we propose a mixed-integer-linear-programming formulation to determine the optimal spare cell positions. Experimental results show that our algorithm can averagely achieve 17--33% and 1.77--2.61X better quality of spare cell insertion than that of the existing spare cell insertion algorithms, UniSpare [10] and PostSpare [22, 26], on the tested real designs with 1--5% spare cell insertion rates.