Thermal phenomena occurring along test execution at the final stages of the manufacturing flow are considered as a significant issue for several reasons, including dramatic effects like circuit damage that is leading to yield loss. This paper tries to redeem those bad guys in order to exploit them to improve the test quality, reducing the overall test cost without affecting the yield.

This work investigates the interrelation of performance and robustness against variability in industrial microprocessor designs. A novel analysis technique for variation-sensitive hardware and two figures of merit to quantify the robustness of a design against variations are proposed. Together with a multi-stage STA this enables an efficient application of low-V T cell insertion and pulsed latch design to compensate for within-die delay variations. For the same speed margin of 5% on design level, a pulsed latch design of an ARM926 microprocessor shows a 2.5× higher robustness compared to a MS-FF design with selective low-V T cell insertion.

Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub- 100nm technologies. In this work we investigate the variability of flip flop race immunity in 130nm and 90nm low power CMOS technologies. An on-chip measurement technique with resolution of ˜1ps is used to characterize hold time violations of flip flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Statistical die-to die variations of hold time violations are measured various register-to-register configurations and show overall 3σ die-to-die standard deviations of 12–16% Mathematical methods to separate the measured variability between systematic and random variability are discussed, and the results presented. They show that while systematic variability is the major issue in 130nm, it is significantly decreased in 90nm technology due to better process control. Another important point is that the race immunity decreases about 30% in 90nm, showing that smaller clock skews can lead to violations in 90nm.

Resonant tunneling devices and circuit architectures based on monostable-bistable transition logic elements (MOBILEs) are promising candidates for future nanoscale integration. In this paper, the design of clocked MOBILE-type threshold logic gates and their application to arithmetic circuit components is investigated. The gates are composed of monolithically integrated resonant tunneling diodes and heterostructure field-effect transistors. Experimental results are presented for a programmable NAND/NOR gate. Design related aspects such as the impact of lateral device scaling on the circuit performance and a bit-level pipelined operation using a four phase clocking scheme are discussed. The increased computational functionality of threshold logic gates is exploited in two full adder designs having a minimal logic depth of two circuit stages. Due to the self-latching behavior the adder designs are ideally suited for an application in a bit-level pipelined ripple carry adder. To improve the speed a novel pipelined carry lookahead addition scheme for this logic family is proposed.

Resonant tunneling transistors (RTTs) and linear threshold gates based on monostable-bistable logic transition elements (MOBILEs) are promising candidates for nano-scale integrated circuits. In this paper the design methodology of RTT logic gates is discussed and experimental results of a monolithically integrated NAND-NOR gate are presented. To exploit the computational functionality of threshold logic circuits a depth-2 full adder and a bit-level pipelined ripple carry adder are proposed.

A large number of devices, a limitation of wiring, and very low power dissipation density are design constraints of future nanoelectronic circuits composed of quantum-effect devices. Furthermore, functional integration, which is the possibility of exploiting quantum effects to obtain a function specific behavior, becomes a core design principle. This paper analyzes the effect of this technological progress on the design of nanoelectronic circuits and describes computational paradigms revealing novel features such as distributed storage, fault tolerance, self-organization, and local processing. In particular, linear threshold networks, the associative matrix, self-organizing feature maps, and cellular arrays are investigated from the viewpoint of their potential significance for nanoelectronics. Although these concepts have already been implemented using present technologies, the intention of this paper is to give an impression of their usefulness to system implementations with quantum-effect devices.