This paper presents a testable architecture for FSM synthesis. The transfer, synchronizing and distinguishing sequences are obtained simultaneously by adding extra edges, if necessary, and their associated inputs and outputs to the original FSM. The algorithm that achieves this minimizes the number of extra edges that make a machine testable. The testable machine has the following properties: (1) transfer sequences of length at most [log/sub 2/n] where n is the number of the states in the machine, to carry the machine from state S/sub i/ to state S/sub j/ for all i and j, (2) a synchronizing sequence of length at most [log/sub 2/n] which sets the machine to a specific state S1, and (3) a distinguishing sequence of length at most [log/sub 2/n]. The states can be observed at the output. Several synthesis benchmark circuits were investigated for area by using the architecture.

Programmable logic arrays (PLAs) provide a flexible and efficient way of synthesizing arbitrary combinational functions as well as sequential logic circuits. They are used in both LSI and VLSI technologies. The disadvantage of using PLAs is that most PLAs are very sparse. The high sparsity of the PLA results in a significant waste of silicon area. PLA folding is a technique which reclaims unused area in the original PLA. This paper proposes a column bipartite folding algorithm based on matrix representation. Heuristics are used to reduce the search space and to speed up the search processes. The algorithm has been implemented in C programming language on a SUN-4 workstation. The program was used to study several large PLAs of varying sizes. The experimental results show that in most cases the proposed algorithm finds optimal solution in a reasonable CPU time.>

A new method for designing a Built-In Self-Test Programmable Logic Array (BIST-PLA) is presented. In the proposed design, the Test Pattern Generator and the Response Evaluator circuits are very simple. The design requires a re-arrangement of the AND (OR) planes on the basis of number of crosspoints in the product (output) lines in the PLA.