Modern cyber-physical systems increasingly rely on computationally demanding applications, particularly at the edge, where Artificial Intelligence-based algorithms are deployed. To meet these demands, industry trends are shifting towards heterogeneous MultiProcessor Systems on Chip (MPSoCs), which must also satisfy strict real-time and functional safety requirements. A major challenge in such systems is memory contention, where multiple processing units compete for shared memory resources, affecting application performance and the accurate estimation of Worst-Case Execution Times (WCETs). Traditional static analysis becomes impractical as system configurations grow in complexity. This work presents the design of an analysis and optimization framework for real-time systems that re-evaluates WCET estimates based on system configurations to reflect the impact of memory contention on heterogeneous platforms. The proposed method estimates new WCETs using Quantile Regression Neural Networks (QRNNs), which infer memory contention from Event Monitor data. Experimental results reveal that QRNN models must be system-specific for accurate predictions and that memory access patterns significantly affect model generalization. Two strategies are proposed: using generic models for simplicity or task-specific models for higher accuracy. Despite some potential underestimations, QRNNs maintain a strong correlation with actual observed contention, enabling effective worst-case scenario identification. Furthermore, a comparative analysis highlights the superior scalability of the estimation-based approach over empirical measurements, especially in large system optimization processes where performance can be easily enhanced by at least two orders of magnitude, making it a practical solution for real-time system design and analysis.

Abstract The current trend in industrial applications is evolving towards heterogeneous platforms that integrate multiple processors and specialized accelerators within a single MPSoC (MultiProcessor System on Chip). Simultaneously, many of these applications have stringent timing requirements that must be met through the appropriate management of concurrency, synchronization, and the deployment of activities across the available computing elements in a distributed environment. In this context, Robot Operating System 2 (ROS 2) is gaining importance as a middleware for distributed systems in the automotive industry. This paper presents the real-time modeling and analysis of a smart mobility application running on a testbed based on MPSoC processors and ROS 2. While a comprehensive analysis of the use case under different configurations is presented, the main contribution is to provide the scientific community with a detailed generic model. This model serves as a benchmark for testing current and future techniques for the modeling, analysis, and optimization of real-time systems based on heterogeneous platforms while highlighting some challenges to be addressed.

The ever increasing computing demands in embedded systems is driving the adoption of hardware accelerators such as GPUs , which offer powerful platforms that can compute parallel workloads efficiently. Relevant critical applications that benefit from such platforms, for instance autonomous driving , usually impose additional real-time requirements that must be met to guarantee the correctness of the systems. In this paper, we propose exploiting readily available and extensively validated techniques to model and analyze real-time systems with GPUs . Specifically, we propose a methodology to employ the MAST model to characterize such systems, and different variants of the Offset-Based Response-Time Analysis techniques to validate the real-time requirements. We verify our approach with a real industrial application sourced from the railway industry . Through a comprehensive evaluation involving synthetic and real task-sets, we characterize the applicability of the approach, and we also show how estimated worst-case response times are aligned with real measurements up to 87.2%.

This paper considers the offline assignment of fixed priorities in partitioned preemptive real-time systems where tasks have precedence constraints. This problem is crucial in this type of systems, as having a good fixed priority assignment allows for an efficient use of the processing resources while meeting all the deadlines. In the literature, we can find several proposals to solve this problem, which offer varying trade-offs between the quality of their results and their computational complexities. In this paper, we propose a new approach, leveraging existing algorithms that are widely exploited in the field of Machine Learning: Gradient Descent, the Adam Optimizer, and Gradient Noise. We show how to adapt these algorithms to the problem of fixed priority assignment in conjunction with existing worst-case response time analyses. We demonstrate the performance of our proposal on synthetic task-sets with different sizes. This evaluation shows that our proposal is able to find more schedulable solutions than previous heuristics, approximating optimal but intractable algorithms such as MILP or brute-force, while requiring reasonable execution times.

We present here the main features and lessons learned from the first edition of what has now become the ECRTS industrial challenge, together with the final description of the challenge and a comparative overview of the proposed solutions. This verification challenge, proposed by Thales, was first discussed in 2014 as part of a dedicated workshop (FMTV, a satellite event of the FM 2014 conference), and solutions were discussed for the first time at the WATERS 2015 workshop. The use case for the verification challenge is an aerial video tracking system. A specificity of this system lies in the fact that periods are constant but known with a limited precision only. The first part of the challenge focuses on the video frame processing system. It consists in computing maximum values of the end-to-end latency of the frames sent by the camera to the display, for two different buffer sizes, and then the minimum duration between two consecutive frame losses. The second challenge is about computing end-to-end latencies on the tracking and camera control for two different values of jitter. Solutions based on five different tools - Fiacre/Tina, CPAL (simulation and analysis), IMITATOR, UPPAAL and MAST - were submitted for discussion at WATERS 2015. While none of these solutions provided a full answer to the challenge, a combination of several of them did allow to draw some conclusions.

The demands for high performance computing with a low cost and low power consumption are driving a transition towards multi-core processors in many consumer and industrial applications. However, the adoption of multi-core processors in the domain of real-time systems faces a series of challenges that has been the focus of great research intensity during the last decade. These challenges arise in great part from the non real-time nature of the hardware arbiters that schedule the access to shared resources, such as the main memory. One solution proposed in the literature is called Memory Centric Scheduling, which defines a separate software scheduler for the sections of the tasks that will access the main memory, hence circumventing the low level unpredictable hardware arbiters. Several Memory Centric schedulers and associated theoretical analyses have been proposed, but as far as we know, no actual implementation of the required OS-level underpinnings to support dynamic event-driven Memory Centric Scheduling has been presented before. In this paper we aim to fill this gap, targeting cache based COTS multi-core systems. We will confirm via measurements the main theoretical benefits of Memory Centric Scheduling (e.g. task isolation). Furthermore, we will describe an effective schedulability analysis using concepts from distributed systems.

This paper develops an offset-based response-time analysis technique for analyzing complex distributed real-time systems where processing and communication resources use the time-partitioning strategy to isolate the operation of separate software components. Time partitioning may be provided in the processors by an ARINC 653 compliant operating system, and in the networks via the TTP communication protocol. The software components executed by the system may themselves be distributed and complex, composed of many concurrent tasks and with one or more end-to-end flows that may have end-to-end timing requirements. The developed analysis supports hierarchical scheduling where a primary scheduler performs time partitioning into separate partitions, and secondary fixed-priority schedulers dispatch the different concurrent tasks inside each partition. It also supports end-to-end flows that are either synchronized with the partition schedule or not. This is the first time that this kind of analysis is developed. An evaluation of an improvement introduced in the analysis is discussed. Two representative case studies are described.

Real-time distributed systems contain end-to-end flows, which are distributed actions composed of sequences of tasks activated through messages. Such flows usually have an end-to-end deadline but the internal tasks and messages do not have specific timing requirements. However, if EDF schedulers are used, it is necessary to assign scheduling deadlines to tasks and messages, which is usually done by distributing the end-to-end deadline among them. Distributed systems may have synchronized global clocks or non-synchronized local clocks. This work studies the influence of the clocks, global or local, on the deadline-assignment algorithms. A study on the poor performance observed for EDF schedulers with local clocks is presented. Then, a significant optimization of the assignment algorithms is shown, in which an amount of end-to-end deadline larger than the established timing requirement is distributed among tasks and messages. With this technique, two new algorithms for deadline-assignment are proposed, showing that they outperform the existing ones by up to 23 percent of processor utilization in the case of local clocks. Finally, the influence of release jitter in this kind of EDF systems and the positive effects of eliminating it are also studied.

The increasing acceptance of the Earliest Deadline First (EDF) scheduling algorithm in industrial environments, together with the continued usage of Fixed Priority (FP) scheduling is leading to heterogeneous systems with different scheduling policies in the same distributed system. Schedulability analysis techniques usually consider the entire system as a whole (holistic approach), with only one preestablished scheduling policy in all the resources. In this work, composition mechanisms will be presented that enable us to combine different FP and EDF response-time analysis techniques for checking the schedulability of heterogeneous systems. Additionally, priority and scheduling deadline assignment techniques will be combined into a new algorithm called HOSPA (Heuristic Optimized Scheduling Parameters Assignment), for optimizing the assignment of priorities and scheduling deadlines to tasks and messages in heterogeneous distributed hard real-time systems.