In this work we present a wide-band amplifier that uses a novel analog pre-distioriton technique based on the quantized-analog (QA) signal processing. Such a technique is exploited to reach an almost rail-to-rail output swing with low distortion compatible with optical driver applications. Based on post layout simulations a 36 GHz −3 dB bandwidth prototype, integrated in 28 nm CMOS technology, shows a 3% Total Harmonic Distortion for 2 V peak-to-peak differential output swing at 1 GHz. The circuit operates under a 1.2 V supply voltage with a dynamic power consumption of 152 mW.

An open-loop baseband filter with bandwidth of 1GHz suitable for a receiver operated in the 5G high frequency band (above 24GHz) is presented. The filter is based on a gain boosted Common Gate topology that implements a 2ndorder low-pass filter in the current domain. A frequency-dependent active negative capacitance circuit is used to boost the quality factor of the filter. This not only improves in-band flatness but also increases out-of-band selectivity. A test chip has been realized in 28nm CMOS technology. The filter bandwidth can be programmed from 650 MHz to 1 GHz and the current gain changed by 14 dB, with the power dissipation scaling from 11 mW to 5 mW. In-band IIP3 is +2 dBm and the input noise integrated from 10 MHz to 1 GHz is lower than 170 μVrms.

A modified noise/nonlinearity cancellation low-noise transconductance amplifier (LNTA) based on an inductively degenerated common-source stage is proposed to improve linearity. The linearity of the proposed LNTA is analyzed using the Volterra series yielding closed-form equations for the third-order input intercept point (IIP3) that shows excellent matching with the simulation results. The derived equations for noise figure (NF) and IIP3 are simple enough to be used for design optimization. Calculations and simulation results show that the proposed LNTA is more linear than a conventional one, while NF approximately remains unchanged. Another feature of the proposed noise-canceling LNTA is that no additional baseband recombination stage is needed, leading to reduced complexity in the receiver baseband stage. The NF and out-of-band (OOB) IIP3 of the receiver is about 3.3 dB and more than 20 dBm, respectively. The receiver consumes 10.5 mA from 1.8-V supply voltage. The current consumption of the LO divider is 6.5 mA from a dedicated 1-V supply voltage.

Minimizing the dissipated power of RF transceivers is the primarily target to meet the requirements of wearable wireless sensor networks (W-WSN). This paper presents an Ultra-Low Power (ULP) receiver with RF performance exceeding the requirements of the intended application. Thanks to the highly efficient current-reuse Low Noise Amplifier (LNA), followed by a passive mixer, the single-ended 2.4 GHz RF input is down-converted to a low-IF. To generate 25% quadrature LO signals, a high-swing complementary current-reuse Class-C VCO, operating at twice the desired frequency, is followed by a frequency divider-by-two. Furthermore, complex channel selection filtering with center frequency and passband of 2 MHz and 1 MHz respectively is performed utilizing the Gm-boosted Common-Gate baseband stage immediately following the mixer. The proposed receiver is designed and simulated in 40 nm CMOS technology. The entire receiver consumes only 220 μW from 0.8 V supply voltage. It shows DSB-NF of 7.5 dB, conversion gain of 50 dB and image rejection of 20 dB. The proposed design represents almost two times better power efficiency with respect to the state-of-the-art with better or equal RF performance.

To meet the requirements of wearable wireless sensor networks (W-WSN), the power dissipation of the RF transceiver has to be drastically reduced. This paper presents an ultra-low power LNA with RF performance exceeding the requirement of the intended application. By reusing the current several times and employing passive gm boosting, the LNA input impedance is reduced by a factor of 24 compared to a single transistor using the same current. The resulting power consumption is only 30μW from a 0.8V supply. Simulation results in 40nm TSMC CMOS technology show NF of 3.3dB and gain of 14.2dB at 2.4GHz. Using a widely accepted FOM for LNAs, the proposed circuit is two times better than the best previously published one.

A fully differential 0.35-/spl mu/m CMOS LNA plus mixer, for GPS applications, using no external component apart from an input balun, has been realized. The LNA makes use of an inductively degenerated input stage and a resonant LC load, featuring 12% frequency tuning, accomplished by a MOS varactor. The mixer is a Gilbert cell type in which an NMOS and a PMOS differential pair, shunt together, realize the input stage. This topology allows one to save power for given mixer gain and linearity. The front-end measured performances are: 40-dB gain, 3.8-dB NF, -25.5-dBm IIP3, 1.3-GHz input frequency, 140-MHz output frequency, with 8 mA from a 2.8-V supply.

A low-power CMOS continuous-time filter is presented. The filter implements a linearization technique which consists of compensating the driver nonlinearity with an opposite load nonlinearity. This results in requiring a lower overdrive to MOS devices and so in power saving. In addition to this the filter features other characteristics which allows one to reduce power consumption. They are: no parasitic poles, no CMFB, no body effect. Finally using digital tuning the performance is optimized for any operation condition. A prototype cell has been designed in a standard 0.5 /spl mu/m CMOS technology. With a pole frequency in the range 13 MHz-83 MHz (Q=1), the cell features a linear range (1%THD) of 400 mVpp from a 3.3 V supply. The parasitic capacitance is kept lower than 20% of the total capacitance. The power consumption in the tuning range varies from 6 mW to 16 mW.

A 4th-order bandpass switched-capacitor (SC) filter to be used as a part of an implantable device has been designed. The power consumption reduction is a key feature of such a system. This has been achieved by using a 1 V supply (SC operation are guaranteed by using the switched-opamp technique). In addition the active devices operate in the subthreshold region. The filter uses a fully differential topology to reduce the clock feedthrough noise and increase the dynamic range. The filter has been designed in a 0.35 /spl mu/m CMOS technology. It operates at 1 kHz sampling frequency and it consumes about 1.2 /spl mu/W.

This paper deals with the realization of a high image rejection (IR) CMOS LNA, tailored to DECT applications. Two topologies are proposed. The first one makes use of a Q-enhancement circuit and provides 15 dB IR with 300 MHz IF, 4.5 dB NF and -13 dBm IIP3. A notch filter loads the second LNA. The results are the following: 30 dB IR, 5.5 dB NF and -10 dBm IIP3. In both cases the frequency control is performed by means of an integrated MOS varactor. These circuits prove to be suitable for highly integrated CMOS receivers employing wideband IF architecture. At the expense of an almost double current consumption with respect to classical LNA, they provide enough image rejection to get rid of off-chip image rejection filters.

A fully differential 0.35μm CMOS LNA plus mixer, tailored to a double conversion architecture, for GPS applications has been realized. The LNA makes use of an inductively degenerated input stage and a resonant LC load, featuring 12% frequency tuning, accomplished by an MOS varactor. The mixer is a Gilbert cell like, in which an NMOS and a PMOS differential pair, shunted together, realize the input stage. This topology allows to save power, for given mixer gain and linearity. The front-end measured performances are: 40dB gain, 3.8dB NF, -25.5dBm IIP3, 1.3GHz input frequency, 140MHz output frequency, with 8mA from a 2.8V voltage supply.

Design considerations regarding the monolithic realization of a high-speed read-out system to be used in future high luminosity colliders such as LHC are presented, System and circuit solution are presented for the first two blocks: the preamplifier and the RC-CR noise shaper. The electronics will be exposed to neutron irradiation and so the required radiation-hard performance is obtained with a design which takes into account the characterisation of the employed bipolar devices before and after neutron radiation,.>

A design approach for realizing high-frequency Gm-C continuous-time filters is proposed and a circuit implementation is presented. The design approach is based on reducing the effects of the finite impedance at each output node by placing a controlled output active load whose value is taken into account in the filter design. The implementation uses a BiCMOS high-efficiency fully-differential transconductor with an all-passive common-mode feedback. Simulation results of a biquadratic low-pass filter with cut-off frequency up to 82 MHz and load capacitance as large as 3pF conclude the paper.>