Massive number of simultaneous Internet of Things (IoT) uplinks strain gateways with interference and energy limits, yet devices often lack neighbors' Channel State Information (CSI) and cannot sustain centralized Mobile Edge Computing (MEC) or heavy Machine Learning (ML) coordination. Classical Bayesian solvers help with uncertainty but become intractable as users and strategies grow, making lightweight, distributed control essential. In this paper, we introduce the first-ever, novel epistemic Bayesian game for uplink power control under incomplete CSI that operates while suppressing interference among multiple uplink channels from distributed IoT devices firing at the same time. Nodes run inter-/intra-epistemic belief updates over opponents' strategies, replacing exhaustive expected-utility tables with conditional belief hierarchies. Using an exponential-Gamma SINR model and higher-order utility moments (variance, skewness, kurtosis), the scheme remains computationally lean with a single-round upper bound of $O\!\left(N^{2} S^{2N}\right)$. Precise power control and stronger coverage amid realistic interference: with channel magnitude equal to $1$ and a signal-to-interference-plus-noise ratio (SINR) threshold of $-18$ dB, coverage reaches approximately $60\%$ at approximately $55\%$ of the maximum transmit power; mid-rate devices with a threshold of $-27$ dB achieve full coverage with less than $0.1\%$ of the maximum transmit power.Under $80\%$ interference, a fourth-moment policy cuts average power from approximately $52\%$ to approximately $20\%$ of the maximum transmit power with comparable outage, outperforming expectation-only baselines. These results highlight a principled, computationally lean path to optimal power allocation and higher network coverage under real-world uncertainty within dense, distributed IoT networks.

Edge devices with limited resources are critical components of modern wireless communication systems. As communication environments become increasingly complex, neural networks are playing a larger role in processing large amounts of data to enable Machine Learning (ML) within these systems. While most FPGA-based accelerators focus on neural network inference, deploying the training phase on resource-constrained edge devices remains a significant challenge. Training on a System on Chip (SoC) that combines ARM processors with FPGA fabric provides unique benefits, including the ability to quickly adapt models to dynamic environments. This work leverages the Tiny Transfer Learning (TinyTL) framework for on-device training, which allows edge devices to continuously adapt neural network models to new data with minimal memory requirements. To the best of our knowledge, this is the first use of a heterogeneous platform to accelerate training using TinyTL. We present the Accelerating TinyTL-based Digital PreDistortion (ATDPD) system, designed to adapt to varying behaviors of power amplifiers in wireless communication systems and implement it on an AMD RFSoC. Our heterogeneous approach achieves comparable training accuracy to ARM-based systems, while accelerating the training phase by more than 20%.

Efficient and reliable resource allocation within densely-deployed massive IoT networks remains a key challenge due to resource constraints among low size, weight and power (SWaP) IoT devices and within the network and limitations of conventional centralized methods under incomplete information. We propose a novel auction-based framework for adaptive resource allocation, combining space-time-frequency spreading (STFS) techniques with Bayesian Game approaches. We introduce novel modified Simultaneous Ascending Auction (mSAA) mechanism tailored to densely-deployed and low-complexity IoT networks, enabling distributed computation and reduced power consumption. By incorporating Bayesian game-based bidding strategies and optimizing dispersion matrices for signal transmission, the proposed approach ensures enhanced channel throughput and energy efficiency. Comparative analysis against traditional auction types, including First-Price and Second-Price Sealed-Bid Auctions, as well as the Vickrey–Clarke–Groves (VCG) mechanism, demonstrates the superiority of mSAA in terms of surplus maximization, revenue efficiency, and robustness in risk-prone bidding environments. Simulation results validate the model’s adaptability to heterogeneous IoT nodes and its potential for dense deployment across different environments and verticals.

The implementation of neural networks (NN) on edge devices enables local processing of wireless data but faces challenges such as high computational complexity and memory requirements when deep neural networks (DNN) are used. Shallow neural networks customized for specific problems are more efficient, requiring fewer resources, and resulting in a lower latency solution. An additional benefit of the smaller network size is that it is suitable for real-time processing on edge devices. The main concern with shallow neural networks is their accuracy performance compared to DNNs. In this paper, we demonstrate that a customized adaptive activation function (AAF) can meet the accuracy of a DNN. We designed an efficient FPGA implementation for a customized segmented spline curve neural network (SSCNN) structure to replace the traditional fixed activation function with an AAF. We compared our SSCNN with different neural network structures such as real-valued time delay neural network (RVTDNN), augmented real-valued time delay neural network (ARVTDNN), and deep neural networks with different parameters. Our proposed SSCNN implementation uses 40% fewer hardware resources and no Block RAMS compared to the DNN with similar accuracy. We experimentally validate this computationally efficient and memory-saving FPGA implementation of SSCNN for digital predistortion of RF power amplifiers using the AMD/Xilinx RFSoC ZCU111 while using less than 3% of the available resources, leaving space for additional real-time processing, while achieving the speed of 221 MHz.

Base stations in cellular networks must operate linearly, power efficiently, and with ever increasing flexibility. Recent FPGA hardware advances have demonstrated linearization using neural networks, however the latency introduced by these solutions is a concern. We present a novel hardware implementation for a low digital cost, high throughput pipelined Real Valued Time Delay Neural Network (RVTDNN) structure with a hardware-efficient activation function. Network training times are reduced by minimizing the training signal samples used, based on a biased probability density function (pdf). The design has been experimen-tally validated using an AMD/Xilinx RFSoC ZCU216 board and surpasses the data throughput of conventional RVTDNN-based DPD while using a fraction of their hardware utilization.

In this paper, we present a novel and effective linearization technique for nonlinear phased array antennas. For large phased arrays, linearization of the array using a single digital predistortion (DPD) is inevitable since one digital path is upconverted and feeds several RF transmission paths, each of which is connected to a power amplifier (PA) and an antenna element. However, a critical issue is that the PA characteristics can vary considerably within an array. Thus, linearizing individual PAs with one DPD is rather challenging. We formulate and solve an optimization problem that corresponds to jointly minimizing the maximum residuals between the input to the array and the output of individual PAs. We demonstrate that the proposed technique outperforms state-of-the-art linearization solutions while retaining the linear gain of the array.

Massive-MIMO and beamforming techniques have long been proposed as a means of increasing cellular network capacity and improving signal to interference ratio performance. The implementation of such systems requires a large number of signal transmission paths. To realize this, a distributed array of power amplifiers (PAs) is likely to be needed. These PAs will possess similar, but unique, characteristics which will alter over time independently due to temperature drift and component ageing. In order to operate all PAs in both a linear and efficient fashion a linearisation technique, such as Digital Pre-Distortion (DPD), must be used. DPD algorithms benefit from reconfigurability, low latency and power efficiency, all traits associated with Field Programmable Gate Arrays (FPGAs). This demonstration shows how an FPGA, specifically a ZYNQ System on a Chip (SoC), can be used in tandem with a transceiver board, the FMCOMMS2, to implement a DPD system.