Demo Data from EDBT 2026 / reviewers in the wild / expert
Samuel Chuquillanqui
dblp:58/10970 · also Samuel Heli Chuquillanqui Bernaola
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 1983
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 84% Integrated circuit design · 16% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.0 | 2 | 1983 | Internal connection problem in large optimized PLAs · DAC 1983 PAOLA: A tool for topological optimization of large PLAS · DAC 1982 |
Electronic design automation › logic synthesis › programmable logic array
PLA optimization |
0.0 | 1 | 1983 | Internal connection problem in large optimized PLAs · DAC 1983 |
Integrated circuit design
VLSI design |
0.0 | 2 | 1983 | Internal connection problem in large optimized PLAs · DAC 1983 PAOLA: A tool for topological optimization of large PLAS · DAC 1982 |
Methods — techniques the papers use, named apart from their topics
topological optimization · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1983 | Internal connection problem in large optimized PLAs
Samuel Chuquillanqui |
DAC | 1 |
| 1982 | PAOLA: A tool for topological optimization of large PLASabstractThis paper presents a tool, called PAOLA, for optimizing the layout of large PLAs used as decoders in VLSI systems. Samuel Chuquillanqui, Tomás Pérez Segovia |
DAC | 1 |