Open-loop floating inverter amplifier (FIA) is widely used in noise shaping filter in SAR ADCs. However, its gain suffers from PVT variation, which primarily affects the shaping factor. Traditional trimming method adjust its gain by increasing or decreasing the effective reservoir capacitor. While adding additional I/O and cumbersome testing, the mere adjustment of reservoir capacitor also faces numerous limitations. This work presents a onetime self-calibrated scheme for FIA in noise shaping SAR ADCs, with neglectable dynamic power. Implementation of calibration adopt a coarse auxiliary cDAC, with most of remaining circuit reusing in main SAR ADC, indicating the cost advantage our design. Simulation results shows that for a 16× designed gain, the original gain fluctuated from 9.8× to 19×. Proposed calibration performed well at stabilizing gain at 16±0.5× under most of PVT corners. The scheme could refer to any other N× gain as well.

This paper presents a high-precision active-passive continuous-time Delta-Sigma Modulator (CTDSM) based on negative-R compensation technology, with a passive integrator in its first stage. Negative-R is used to alleviate the limitations of passive integrator in high-precision CTDSM applications, including integration pole drift, load effect, gain attenuation. Furthermore, in order to improve the robustness of negative-R in the integrator, an analog calibration technique is proposed. The transistor-level prototype is implemented in 180nm CMOS and the simulation results show that the proposed modulator’s signal-to-noise and distortion ratio (SNDR) is 100.2dB over a bandwidth (BW) of 24kHz, with a FoMs value of 179.4 dB.

In a network processor, multiple processor cores share a centralized memory, whose latency and bandwidth easily become bottlenecks. Unlike CPUs or GPUs, network processors serve for packets and do not execute programs in units of tasks or processes. Therefore, a dedicated scheduling policy of centralized memory must be designed for packets. In this paper, we propose an efficient memory access scheduling policy when a great number of packets access centralized memory. Compared with traditional scheduling strategies such as synchronous RR and synchronous DRR, it performs dynamic scheduling based on real-time situations of packets and calculates the scheduling result through the packet status matrix. As a result, it can reduce the average memory access latency by 29.44%, thereby increasing the packet bandwidth of the network processor system by 5.74%.

This paper presents a continuous-time (CT) Sturdy multistage noise-shaping (SMASH) Delta-sigma Modulator (DSM), proposing a quantization noise extraction scheme without traditional analog delay matching circuits, improving modulator’s robustness and relaxing performance requirement for building blocks. For power-efficiency, the first-stage’s quantizer is designed with a 5-bit Voltage Controlled Oscillator (VCO) based analog-to-digital converter (ADC) and the second-stage’s quantizer is implemented by a 5-bit first-order noise-shaping (NS) successive approximation register (SAR) ADC. A transistor-level prototype is implemented in 40nm CMOS and the simulation results show that the modulator’s SFDR and SNDR is 85.8dB and 70.4dB respectively over a bandwidth (BW) of 20MHz while consuming 7.13mW, leading to an excellent FoM of 164.9dB.

In recent years, deep learning methods make a big difference in side-channel attack (SCA) community especially in the profiled scenario. Multiclass classification method is the common way to complete such classification task. In this article, we propose a novel SCA method utilizing multilabel classification from bit-to-byte view. Accordingly, each leakage trace has eight labels when considering a byte. The experimental results on several datasets show that our multilabel classification method is efficient and even performs better in some situations compared with the original multiclass classification model while model complexity is much reduced. Besides, our multilabel model can be seen as ensemble of monobit models and we verify the ensemble effect experimentally.

This paper presents the modeling and design consideration of a time-based ADC architecture that uses VCOs in a high-linearity, 2nd-order noise-shaping delta-sigma ADC. Instead of driving the VCO by a continuous analog signal, which suffers from the nonlinearity problem of the VCO gain, the VCO is driven in an intrinsically linear way, by a time-domain PWM signal. The two discrete levels of the PWM waveform define only two operating points of the VCO, therefore guaranteeing linearity. In addition, the phase quantization error between two consecutive samples is generated by a phase detector and processed by a second VCO. Together with the output of the first VCO, a MASH 1-1 2nd-order noise-shaping VCO-based time-domain delta-sigma converter is obtained. Fabricated in 90 nm CMOS technology, the SFDR is larger than 67 dB without any calibration for a 20 MHz bandwidth.