Cardiovascular diseases remain a leading global health threat, with arrhythmia being a key early indicator of cardiac abnormalities. The need for continuous cardiac monitoring has driven demand for portable, low-power arrhythmia detection systems. This paper presents a low-power mixed-precision System-on-Chip (SoC) solution designed for arrhythmia detection using 12-lead electrocardiogram (ECG) signals. The proposed approach employs a dynamically reconfigurable convolutional neural network (CNN) architecture with flexible hyperparameters, enhancing hardware adaptability while reducing resource overhead and power consumption. At the computation level, an 8-bit and 16-bit mixed-precision floating-point multiplier is introduced to effectively balance arithmetic accuracy and energy efficiency. Furthermore, clock gating and multi-threshold voltage techniques are employed at the digital back-end to further reduce the power consumption of the chip. Through system-level and module-level optimization, the proposed chip design is of great significance for enabling low-power arrhythmia detection in power-constrained portable medical devices.

Alzheimer’s disease (AD) is an irreversible neurodegenerative disorder that remains difficult to cure. However, early screening and timely intervention can significantly slow its progression. Traditional AD detection methods are plagued by high misdiagnosis rates, low hardware integration, and lack of diagnostic diversity. To address these challenges, this paper proposes a configurable System-on-Chip (SoC) design based on a multimodal fusion Artificial Neural Network (ANN) for high-precision diagnosis. The proposed design integrates Electroencephalogram (EEG) and Magnetic Resonance Imaging (MRI) signals. First, a discretized reverse training method was employed to compress the features of the MRI images and reduce the input dimensionality. Second, intra-layer parallel computation and inter-layer pipeline scheduling were implemented to enhance the computational throughput. Finally, a dynamic configuration strategy for Processing Elements (PE) was introduced to optimize the hardware resource utilization. The proposed design achieves a six-fold improvement in throughput and provides multiple diagnostic approaches for AD. In conclusion, this work provides an efficient and scalable hardware solution for the early screening and dynamic monitoring of AD, which is expected to promote the development of portable and intelligent AD diagnostic devices and has good prospects for clinical transformation and application.

Device authentication protocols based on a strong physical unclonable function (PUF) show promise for enhancing Internet of Things security. However, a strong PUF is vulnerable to machine learning (ML) attacks. This paper proposes a Feistel structure sequential obfuscation-based PUF (Feistel-PUF) to resist ML attacks. When the PUF is obfuscated by the Feistel structure, the challenge-response relationship resembles that of sequential logic circuits. Specifically, each response depends on both current and historical challenges, thereby significantly increasing the complexity of the challenge-response mapping. Experimental results showed that even with 1 million collected challenge response pairs, the prediction accuracies of ML attacks on Feistel-PUF remained at approximately 50%. Notably, the obfuscation process excluded response data, thereby preserving the randomness, reliability, and uniqueness of PUF with negligible performance degradation. The Feistel structure was iteratively reused for sequential obfuscation processing, maintaining constant and minimal hardware overhead. We propose a novel approach that combines the Feistel-PUF with an authentication protocol. This system synchronizes obfuscation parameters during the initial registration phase and implements dynamic updates throughout the authentication process. This approach allows the obfuscation structure to be made public, thereby overcoming the reliance on structure or algorithm secrecy in traditional dynamic challenge obfuscation schemes. The security of the protocol was confirmed by subjecting it to ProVerif verification and security analysis.

Addressing security threats faced by high efficiency video coding (HEVC) video devices in open deployment environments, this article proposes a HEVC Transform and Quantization (TQ)-based Software Physical Unclonable Function (TQ-SPUF). By overclocking the HEVC TQ module, this function induces clock violations on the critical path, thereby generating a stable and unique device fingerprint. Meanwhile, a two-stage postprocessing scheme combining majority voting and butterfly-xoroperations is employed to generate stable and uniform device fingerprints. Based on the proposed TQ-SPUF, a lightweight challenge-response authentication protocol was designed to achieve device identity binding. Furthermore, the PUF-gated session key is utilized to drive a dual-perturbation selective encryption scheme, which introduces both fixed- and random-position perturbations into the I-frame network abstraction layer units. In this way, semantic information exploitable was effectively disrupted, thereby preventing content recovery or tampering. Experimental results show that the proposed TQ-SPUF achieves 98.84% randomness and 49.15% uniqueness, passing part of the NIST test. Moreover, the encrypted videos exhibit an average peak signal-to-noise ratio (PSNR) of 10.4313dB and an average structural similarity index measure (SSIM) of 0.2935. This indicates that the encrypted content is visually incomprehensible, thereby achieving video anti-tampering protection.

This brief proposes an average-6.5T twin cell for a deep sub-micrometer 64kb SRAM, which utilizes two identical asymmetric single-ended (SE) 6T cells in a column with a shared read assist device to improve read margin and write ability. It enables the SRAM to achieve read-disturb-free, near/sub-threshold operation and compact array layout, resulting in area and energy efficiencies. The average-6.5T SRAM test chip is fabricated using a 65 nm CMOS logic process. Its cell area shows only 5.6% overhead compared to the standard 6T cell, and is smaller than that of other low-voltage SRAMs. Measured full read and write functionality is performed with VDD down to 0.39 V, which is lower than that of standard 6T and 8T SRAMs. In addition, its minimum energy point of 6.3 pJ is obtained at 0.48 V.

In the era of intelligent computing, with the aid of Internet of Things (IoT) technology, artificial intelligence (AI) chips can be embedded at the terminal, object, edge, and cloud levels, ultimately achieving the vision where there is computation, there is AI intelligence. This not only enhances the efficiency of production and daily life but also exponentially increases the risk of privacy information leakage within AI models. This article leverages the characteristics of strong physical unclonable functions (PUFs), in which the inherent feature information is hidden in physical variations and difficult to steal, to design a security protocol based on strong PUFs that provides effective protection for AI model parameters in the IoT environment. The protocol treats AI model parameters as responses and selects challenges capable of generating these responses. Since the responses generated by the challenges can be considered as randomly generated, transmitting the challenges does not disclose the response information, thus avoiding the risk of parameter hacking. Additionally, the protocol utilizes machine-learning modeling techniques and lightweight encryption technologies to reduce the storage costs for identity information and the computational overhead of encryption operations. Through a security analysis of the protocol, it demonstrates that even under ideal attack conditions, the proposed protocol can resist various attacks. By using formal verification with the ProVerif tool, it confirms the security of the protocol flow and the effective protection of private information.

With the increasing number of devices in the Internet of Things (IoT), security has become a necessary feature. Compared to traditional key encryption methods, IoT device authentication protocols based on strong Physically unclonable function (PUF) have the advantage of being difficult to leak and tamper with. In addition, the protocol can enhance the resistance of strong PUFs to machine learning (ML) attacks by encrypting private information. However, the quality of the authentication is strongly related to the stability of the generated responses. If a large cost is incurred to improve the stability of the strong PUF, it will consume the already scarce resources of the device. This article proposes a challenge screening strategy to improve the response stability of a commonly used strong PUF, arbiter PUF (APUF). First, a precise modeling method of APUF is carried out using the logistic-regression ML algorithm. Subsequently, random noise is injected into the challenges or PUF mathematical model and then calculated to estimate whether a stable response can be produced. Finally, stable challenges are used for IoT device authentication, while the threshold of the protocol is increased in parallel. Experimental verification shows that the proposed strategy can increase the stability of APUF responses to 100% at different temperatures. Furthermore, it does not consume hardware overhead at the device end, which is of particular significance for applications in resource-constrained conditions.

Unmanned Aerial Vehicle (UAV) swarms networks have gained increasing significance in daily life and work. However, current UAV authentication protocols face critical security challenges such as high computational overhead, complex key management, and vulnerabilities to network attacks. This paper proposes a hierarchical authentication protocol that enhances resilience against attacks while maintaining ultra-low overhead. The protocol employs a two-tier mutual authentication architecture, comprising authentication between the base station and the server, and between the server and the UAV leader. This design effectively reduces the risk of single-point failure and improves scalability in large-scale swarm scenarios. Physical unclonable function (PUF) technology establishes secure UAV identities, combined with randomized leader election enhance security, reduce overhead, and increase attacker localization complexity. This paper presents a lightweight cryptographic strategy that combines hash-based challenge encryption and XOR-based response obfuscation to disrupt predictable PUF challenge-response mappings, countering machine learning (ML)-based modeling attacks. The proposed protocol passes security tests using ProVerif and Scyther. The scheme achieves 58.21% lower communication costs than existing approaches, with an authentication overhead of 58.04 μs.

The novel nonvolatile computing-in-memory (nvCIM) technology enables data to be stored and processed in situ, providing a feasible solution for the widespread deployment of machine learning algorithms in edge AI devices. However, current nvCIM approaches based on weighted current summation face challenges such as device nonidealities and substantial time, storage, and energy overheads when handling high-precision analog signals. To address these issues, we propose a resistive random access memory (RRAM)-based binary convolution macro for constructing a complete binary convolutional neural network (BCNN) hardware circuit, accelerating edge AI applications with low-weight precision. This macro performs error compensation at the circuit level and provides stable rail-to-rail output, eliminating the need for any ADCs or processor to perform auxiliary computations. Experimental results demonstrate that the proposed BCNN full-hardware computing system achieves on-chip recognition accuracy of 90.7% (98.64%) on the CIFAR10 (MNIST) dataset, which represents a decrease of 0.98% (0.59%) compared to software recognition accuracy. In addition, this binary convolution macro achieves a maximum throughput of 320 GOPS and a peak energy efficiency of 578 TOPS/W at 136 MHz.

Security and cost efficiency are of utmost importance for embedded processors when it comes to limiting hardware resources in IoT applications. This brief presents a security reduced instruction set computer-five (RISC-V) specific instruction set extension (ISE) designed based on hardware-assisted orthogonal obfuscation for hardware security. The orthogonal obfuscation defines an architecture geared toward high-security processors that supports a Pay-Per-ISE function using a key management unit (KMU), thus capable of supporting the customization of the key for a user’s partially authorized ISE and controlling the unlocking of the specific ISE. The proposed security RISC-V test chip is fabricated in a 65-nm CMOS technology with a core area occupying about 0.739 mm2. The measured results demonstrate that our processor realizes the instruction set authorization function. The results show an average power of 52.8 mW at 1.2 V, a hardware overhead of <3% at 50 MHz, and a 30% improvement in security.

This paper presents an oil painting authentication scheme based on physical unclonable function (PUF), aiming to address the high cost and cumbersome process associated with existing oil painting authentication technology. The proposed technique utilizes oil painting texture deviation to generate highly secure PUF information, serving as the digital fingerprint of the oil painting for authentication. The captured oil painting image is first preprocessed using histogram equalization technology to mitigate the influence of light intensity in the shooting environment. Subsequently, the feature extraction model based on local binary pattern (LBP) calculates the preprocessed image, yielding a sequence of 130 feature values containing unique information about oil painting texture deviation. A PUF key algorithm is then designed to map the feature value sequence into a 128-bit binary PUF key, uniquely corresponding to a specific oil painting. Furthermore, a PUF-based oil painting authentication protocol is constructed to provide standardized and credible authentication for the art market. Finally, the security and reliability of the PUF key are analyzed. Experimental results demonstrate that the uniqueness of the proposed PUF is 50.03%. Additionally, PUF data successfully passes the NIST random number test, fully proving its excellent randomness.

High-precision miniaturized micromechanical accelerometers are used extensively in the civilian and military fields. A novel self-test-on-chip method and time-multiplexing feedback method for capacitive accelerometers were proposed in this work. The self-test-on-chip circuit can simulate an acceleration signal to test the harmonic distortion without a high-precision shaker table. Using digital timing control, the time-multiplexing feedback can reduce the coupling between the feedback signal and the detection signal. In addition, a low-noise charge sensing and sigma-delta modulator were designed for a high-precision digital output. The interfaced circuit with fully differential topology was fabricated in a$0.35 \mu \text{m}$standard complementary metal-oxide semiconductor (CMOS) process. The integrated accelerometers can achieve a power consumption of 7 mW from a 5 V supply at a sampling frequency of 256 kHz, a noise floor of −140 dBV below 400 Hz. The equivalent input noise voltage density is 250nV/$\surd $Hz, corresponding to a reference voltage of 2.5V. It can achieve an equivalent noise acceleration of$0.14 \mu \text{g}\surd $Hz and a bias instability of$9 \mu \text{g}$at a bandwidth of 400 Hz, a nonlinearity of 0.13% within ±1 g.

This study presents a technique for designing a multimode configurable weak physically unclonable function (PUF) for security-key generation. The PUF cell is based on the maximum gain point deviations of bias-voltage-controlled inverters. By implementing a preselection strategy, the proposed PUF can simultaneously expose all unstable cells under normal voltage and temperature. Owing to the configurable bias circuit, the PUF cell can be biased at three operating modes, namely, traditional inverter (INV), current-starved inverter (CSI), and power gating (PG). The measurement results from a 65-nm prototype show that the proposed PUF has the following outstanding features: 1) it has a compact cell layout with a minimum feature size of 966 F2; 2) an autocorrelation function of 0.0099 is achieved; and 3) all unstable cells can be eliminated using a preselection procedure, which can drastically reduce the energy and area costs for error correction. In addition, in the CSI mode, the proposed PUF (standard voltage) has maximum frequency and throughput of 714 MHz and 45.7 Gb/s, respectively. Meanwhile, under the INV mode, the worst native bit error rate (low voltage) for 5000 evaluations is only 0.33%, indicating a desirable instability against voltage and temperature variations with a sensitivity coefficient of 1.85%/V and 0.018%/°C, respectively. Moreover, the measured energy efficiency at 0.6 V is 6.83 fJ/bit. Finally, under the PG mode, the standby powers at 0.6 and 1.2 V are only 18 and 86 nW, respectively.

This article presents a novel class of bistable physically unclonable functions (PUFs) for security-oriented applications. The traditional cross-coupled bistable PUF cell is divided into P-net and N-net, wherein the P-net (N-net) multiplexing acts as the shared head (foot), and the N-net (P-net) duplicating multiple acts as the PUF cell. The proposed PUF was fabricated in a Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm process with full-custom design. It can parallelly generate 128-bit identifications (IDs) in one clock cycle owing to the random access word-level readout framework. The measurement results show that the randomness and uniqueness of the proposed PUF are consistent with those of the state-of-the-art works. In addition, the proposed PUF has the following features: 1) the PUF cell is composed only of four nMOS transistors with a minimum feature size of 215-F2; 2) the native bit instability at the golden condition (i.e., 1.2 V, 25 °C) with 500 evaluations is only 2.05%, showing a desirable native stability against supply noise; 3) the bit-error-rate dependences of the voltage and temperature are 3.35%/V and 0.011%/°C, respectively, with the voltage varying within the range 1.0-1.4 V and the temperature varying within the range -40 °C to 125 °C; 4) an autocorrelation function of 0.0049 at a 95% confidence level is achieved and is the lowest reported value to date; and 5) the energy efficiency and throughput at the maximum operating frequency (i.e., 433 MHz) are 99.48 fJ/b and 55.5 Gb/s, respectively.

Soft error protection is a paramount requirement for memories exposed to radiation environment. To satisfy the demand, a radiation-hardened new-quatro 10T memory cell is proposed in this brief, which is immune to single-node upset and also has high resilience to multinode upset while features read-disturbance-free benefiting from its internal quad-node interlocked feedback mechanism. Simulation results show that it provides ample radiation robustness to single event and gives 1.75× improvements in multinode upset tolerance when compared with the previous 12T dual-interlocked storage cell (DICE-12T) bitcell, signifying the higher fault tolerance capability. In addition, the proposed design also achieves 6.48× enhancement in read noise margin when compared with the DICE-12T bitcell while compromising only 2.1× larger area than a reference 6T cell based on a 65-nm logic design rule, exhibiting the superiority in read stability.

A nondestructive column-selection-enabled 10T SRAM for aggressive power reduction is presented in this brief. It frees a half-selected behavior by exploiting the bitline-shared data-aware write scheme. The differential-VDD (Diff-VDD) technique is adopted to improve the write ability of the design. In addition, its decoupled read bitlines are given permission to be charged and discharged depending on the stored data bits. In combination with the proposed dropped-VDD biasing, it achieves the significant power reduction. The experimental results show that the proposed design provides the 3.3× improvement in the write margin compared with the standard Diff-10T SRAM. A 5.5-kb 10T SRAM in a 65-nm CMOS process has a total power of 51.25 μW and a leakage power of 41.8 μW when operating at 6.25 MHz at 0.5 V, achieving 56.3% reduction in dynamic power and 32.1% reduction in leakage power compared with the previous single-ended 10T SRAM.

Emerging physical unclonable function (PUF) circuit designs in the IC supply chain pose not only a challenge to security threats but also a serious concern about hardware efficiency. The existing conventional PUF methods extract intrinsic random physical variation to generate two-valued secret key bits, which lack logical complexity and have poor efficiency in interconnect lines. This paper proposes a multiple-valued logic PUF circuit (MPUF), which focuses on adding logical complexity and minimizing hardware cost by processing on multilevel-cell and interconnect lines. The twins' cell is selected as the MPUF cell to source the multiple-valued physical variation, and the bit-line sharing strategy was integrated to implement the four-valued PUF data. After full-custom designing, the MPUF with 512 cells only needs 16 transmit bit lines. The proposed MPUF chip is fabricated under 65-nm CMOS technology and the core area occupies approximately 0.016 mm2with a 4.9-μm2bitcell size. The measured results show that the MPUF data passed National Institute of Standards and Technology randomness tests, and that it operates 0.1-pJ/b energy efficiency at 1.2 V, ensures randomness and uniqueness with 50.42% hamming distance, and less than 0.04 autocorrelation at 95% confidence level. Compared with other state of the arts, logical complexity improves 50% for resisting power attacks.

The Physical Unclonable Function (PUF) circuit generates a random, unclonable key by extracting random deviations of the manufacturing processes. In this paper, a delay ternary PUF (DT-PUF) circuit scheme based on Carbon Nanotube Field Effect Transistor (CNFET) is proposed. In this scheme, the two inputs and two outputs (2I2O) multi-value delay circuit and the multi-valued arbiter circuit is designed by the threshold controllable CNFET. Then, the ternary signals logic 0, logic 1 and logic 2 transmission delay path is realized by cascading multi-bit 2I2O multi-value delay circuits. Secondly, the delay deviation of the two identical transmission paths is set as the random source. With the help of ternary arbiter, the random delay competes to produce the unclonable ternary PUF output data. Finally, the proposed DT-PUF circuit is designed under 32nm CNFET standard model library, and the circuit is simulated and analyzed by HSPICE. Experiment results show that DT-PUF circuit has the correct logic function, and the distribution is 30.3%@logic 0, 36%@logic 1, 33.7%@logic 2, near ideal about 33.3%.

This brief proposes an ultralow-voltage four-read-port and two-write-port multiported register file with a novel architecture of read word-line sharing strategy for energy/area efficiency. Static read circuits and memory cells with nonminimum channel length are introduced to improve the ultralow-voltage performance. The chip of this register file is fabricated in 65-nm LP CMOS process and occupies the area of 0.019 mm$^{2}$ . Test results show that the minimum operation voltage is 320 mV with its corresponding max frequency 110 KHz. The minimum energy consumption is 0.94 pJ/cycle at the point of 400 mV, 850 KHz, corresponding to 0.15 fJ/port/bit/cycle after normalization. Compared with the state-of-the-art designs, it improves energy efficiency by 25% and saves the area by 58.7%.

Educational robotics has long been proved an effective tool to enhance teaching effectiveness in scientific fields such as mathematics, physics, engineering, and computer science. Teachers working in a robotics classroom, however, face difficulty in the identification of the needs for proper interventions to the students’ learning processes. To tackle this problem, we proposed and implemented an agency architecture which uses software agents to monitor the student activities and robot movements. The implementation is multi-agent based and distributed across a network of student terminals as well as the teacher terminal. As a result, both promising prospects and limitations are revealed in this implementation.

Teachers working in robotics classes face a major problem: how to keep track on individual students' or even small groups' progress in a class of 30-40 students. An agency approach to this problem is based on having sensors to monitor students' interaction, robots' movements, and the construction and programming process of robots. The design can be implemented with the Lego Mindstorms set using the IPPE programming environment. The designed architecture works well for monitoring small groups, but needs further work to support teacher's intervention to an individual student's learning process