In this paper we introduce a new method for the fast evaluation of the elementary functions in single precision based on the evaluation of truncated Taylor series using a difference method. We assume the availability of large and fast (at least for read purposes) memory. We call this method the ATA (Add-Table lookup-Add) method. As the name implies, the hardware required for the method are adders (both two/ and multi/operand adders) and fast tables. For IEEE single precision numbers our initial estimates indicate that we can calculate the basic elementary functions, namely reciprocal, square root, logarithm, exponential, trigonometric and inverse trigonometric functions, within the latency of two to four floating point multiplies.>

As the name suggests, elementary functions play a vital role in scientific computations. Yet due to their inherent nature, they are a considerable computing task by themselves. Not surprisingly, since the dawn of computing, the goal of speeding up elementary function computation has been pursued. This paper describes new hardware based algorithms for the computation of the common elementary functions, namely division, logarithm, reciprocal square root, arc tangent, sine and cosine. These algorithms exploit microscopic parallelism using specialized hardware with heavy use of truncation based on detailed accuracy analysis. The contribution of this work lies in the fact that these algorithms are very fast and yet are accurate. If we let the time to perform an IEEE Standard 754 double precision floating point multiplication be /spl tau//sub /spl times//, our algorithms to achieve roughly 3.68/spl tau//sub /spl times//,4.56/spl tau//sub /spl times//, 5.25/spl tau//sub /spl times//, 3.69/spl tau//sub /spl times//, 7.06/spl tau//sub /spl times//, and 6.5/spl tau//sub /spl times//, for division, logarithm, square root, exponential, are tangent and complex exponential (sine and cosine) respectively. The trade-off is the need for tables and some specialized hardware. The total amount of tables required, however, is less than 128 Kbytes. We discuss the hardware, algorithmic and accuracy aspects of these algorithms.>

A novel Josephson device with many desirable properties/spl minus/fast switching speed, high operation frequency, and low power dissipation/spl minus/has been researched these several years: the Quantum Flux Parametron (QFP). This paper discusses the interconnection problem of QFP circuits, where wire inductance matching and high clock rate restrict the lengths of interconnection wires. A layout model of QFP interconnection wires is clarified, and the effects of wire inductance matching on interconnection area and wire length are analyzed. The limitation comes from the bound of the number of squares of wires, therefore similar effects will exist where wire resistance is bounded. This paper discusses a simple wiring and buffering algorithm for QFP circuits, in which wire inductance is adjusted and the maximum wire length is controlled, to prove that any logic is realizable as a QFP circuit.>

An economical, unbiased, overflow-free rounding scheme for multiplication of multiple-precision floating-point numbers is proposed. The scheme, called pseudorandom rounding, saves multiplications of lower bits and makes use of statistical properties of bits around the least significant bit of products in order to compensate for truncated parts. The method is deterministic, and inputs are commutable. The validity of the rounding is verified by numerical simulation.>

This paper describes the BL addressing mode and the address tag in FLATS2 machine, which is a general-purpose MIMD computer now under construction. The BL addressing mode integrates memory accessing and range checking by hardware. Address tag is a bit in word, which indicates the capability for memory access. Combining them together, efficient memory protection is provided at run-time. It reduces the cost of run-time type checking in Lisp by checking the address tag and the address of a pointer against the range of the region associated to a type, in parallel with the memory access. The arithmetic instructions check the address tags of operands to support the generic arithmetic in Lisp. We can also make use of this scheme to check the number of arguments and multiple return values and to check array-bounds to support faster execution of Common Lisp program. These facilities are not specific to Lisp, so that they can be used more generally than other tagged architectures.

Describes a novel computer architecture, called a cyclic pipeline computer (CPC), which is especially suited for Josephson technologies. Since each Josephson logic device acts as a latch, it is possible to use high-pitch and shallow logic pipelining without any increase in delay time and cost. Hence, both the processor and the main memory can be built from the Josephson devices and can be pipelined with the same pipeline pitch time. The CPC supports multiple instruction/multiple data stream (MIMD) by time-sharing the processor and the main memory among multiple instruction streams. In addition, it employs advanced control to speed up the computation for each instruction stream.>

Functional aspects of a machine called FLATS are described. FLATS aims to efficiently run both numerical and algebraic programs. Overflow free and variable precision arithmetic, table look-up computation, and associative computation based on single-hit content addressed tables are introduced for advanced numerical, algebraic and symbolic computing. Hashing hardware, tag mechanism and hardware list processing are used to realize these features.

Logical circuits using Esaki diodes, and which are based on a principle similar to parametron (subharmonic oscillator element) circuits, are described. Two diodes are used in series to form a basic element called a twin, and a binary digit is represented by the polarity of the potential induced at the middle point of the twin, which is controlled by the majority of input signals applied to the middle point. Unilateral transmission of information in circuits consisting of cascaded twins is achieved by dividing the twins into three groups and by energizing each group one after another in a cyclic manner. Experimental results with the clock frequency as high as 30 mc are reported. Also, a delay-line dynamic memory and a nondestructive memory in matrix form are discussed.