Predictive models based on Pareto fronts are key tools to understand and leverage tradeoffs in electronic circuit and system design. However, their generation conventionally requires the extensive use of numerical simulation and multi-objective optimization methods, resulting in significant computational cost. This cost increases exponentially with the number of parameters, and visualization also becomes an issue as the number of performance metrics increases. In this paper, we present a method to extract predictive models efficiently for electronic subsystems based on Pareto fronts. We use a very fast design and migration software called ID-Xplore™ to generate the performance space of sub-blocks in order to generate Pareto fronts for any block, thereby circumventing the traditional use of numerical optimization and thus accelerating the generation of Pareto-fronts for n-performance. We also combine the Pareto fronts in order to obtain one single Pareto front that represents all specifications, and use the Hyper-Space Diagonal Counting (HSDC) methodology to visualize n-performance Pareto fronts and combine the overall approach to help the designer in the final choice of optimal design points in the design of a state of the art OTA.

This paper proposes a fully-integrated solution for the PI compensation circuits in current-mode DC-DC converters used in automotive applications. In such applications, the switching frequencies are low and hence conventional PI compensation circuits employ large capacitors. The proposed analog/mixed-signal PI comprises an analog proportional amplifier and a digital integrator. The analog proportional amplifier provides the required response time and maintains system stability. The digital integrator block is used to eliminate the output voltage steady-state error. Simulink is used to model the proposed DC-DC buck converter on the system level. The proposed system is verified by full system level simulation. The digital part is synthesized with HDL coder and laid-out using 0.35 μm CMOS technology. The estimated silicon area of the proposed solution is about 0.1 mm2. This result highlights the simplicity and the capacity for integration of the proposed control loop along with its potential for seamless implementation into pre-existing solutions with minor modifications.

Substrate noise coupling due to minority carriers propagation in smart power integrated circuit becomes a critical issue specially for high voltage applications. Computer-Aided-Design modeling methodology for substrate parasitic-immune design was introduced. It is based on constructing a 3D substrate equivalent network. The substrate equivalent network consists of models of diodes and resistors that are capable of preserving the continuity of minority carriers. In this paper, an optimized meshing topology for substrate modeling is introduced. This meshing topology contributes significantly in the extracted component reduction and hence speeds up the simulation while improving the convergence of the simulator. A typical NPN bipolar transistor is used as case study. Comparing the proposed meshing topology to the basic meshing topology, the number of extracted components is reduced by 78% and the simulation time is lowered by 88%. SPICE-like analysis results confirm the accuracy of modeling approach with an acceptable relevant error (<;10%) compared to standard model. With the proposed meshing topology, it is feasible to model the substrate parasitic of more complex smart power integrated circuit.

A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction methodology is introduced by dividing the IC layout into elementary elements to solve the continuity equation for minority carriers in the volume based on the finite-difference method. A substrate parasitic network is derived from the mesh generated through the existing mixed-signal design flow. The induced substrate model is included in circuit simulators such as SPICE to predict the effects of substrate couplings during the design phase. Furthermore, this analysis enables optimization of layout with minimal parasitic effects. By linking the substrate model to the active components, the couplings between the integrated circuit with the substrate parasitic currents can be analyzed during circuit simulations. Simulations and measurements on an high voltage driver reveal consistent results and therefore confirm the validity of the method. Therefore, the approach developed herein is effective to predict parasitic couplings due the injection of minority carriers.

In smart power IC technology, low and high voltage circuits are integrated on the same substrate. The commutation of the high voltage circuits can induce substrate parasitic currents which can severely disturb the operation of the low voltage circuits. The parasitic currents due to minority carriers in the high voltage technology can be significantly high. However, the minority carrier propagation into the substrate is not considered in most of existing circuit simulators. In this paper, a novel computer-aided design tool for substrate parasitic extraction is proposed. A simple circuit with an injecting and a collecting N-wells over a P-substrate is studied. With the distance between the wells varying, the lateral bipolar effect is illustrated. The spectre simulation results of extracted substrate equivalent circuit are compared to a TCAD simulation results. The comparison shows an acceptable relevant error. However, the simulation time was reduced by approximately 1400 times with respect to the TCAD.

This paper presents a structured DC analysis methodology for analog circuit verification. The electrical simulator, usually executed to perform verification, is here replaced by a nonlinear DC solver based on the analysis bipartite graph. The analysis bipartite graph, associated to a circuit, is a formal representation of the circuit DC behavior. Thus, the analysis bipartite graph evaluation provides transistors currents and internal nodes voltages to meet the Kirchhoff's laws in the circuit. Currents and voltages are computed by dedicated operators using the fixed point iteration algorithm. Computed results accuracy is guaranteed by the standard transistor models used within the operators. The proposed verification methodology is efficiently applied on a folded cascode amplifier with several technologies.

In this paper, a simulation-based synthesis tool, AMIGO, for analog cell sizing, is presented. AMIGO is based upon genetic optimization techniques adapted to circuit sizing. A framework has been developed using the TCL/TK language that allows the designer to set the optimization problem, define complex constraint functions, watch the progress of optimization, and finally view the results. To increase design reliability, a sizing-rule pre-processor is incorporated in the tool to automatically generate topology related constraints specific to analog building blocks. Different approaches of using circuit optimizers are demonstrated through the synthesis of three different analog cells: a latched-type comparator, a folded cascode opamp and a switched-capacitor integrator. AMIGO showed to be a successful synthesis tool that can be part of a more general synthesis/migration flow.