This paper presents a fully-CMOS, tunable impulse radio ultra-wideband (IR-UWB) transmitter for high-density implantable neural recording systems. Fabricated in 28 nm CMOS technology, the transmitter features an ultra-compact edge-combining architecture based on a digitally tunable impulse response filter (IRF) occupying only$0.0027~ {\mathrm {\text {m}\text {m} ^{2}}}$. The measured output exhibits a central frequency of$4.5~ {\mathrm {\text {G}\text {Hz} }}$with a 10-dB bandwidth of$3.6~ {\mathrm {\text {G}\text {Hz} }}$, providing robust spectral performance. It achieves$1~ {\mathrm {\text {G}\text {Hz} }}$frequency tunability by adjusting pulse widths from$650~ {\mathrm {\text {p}\text {s} }}$to$800~ {\mathrm {\text {p}\text {s} }}$, ensuring compliance with FCC spectral masks. A current-starved ring VCO (CSRVCO), with a compact$150~ {\mathrm {\mu \text {m} ^{2}}}$layout, serves as the clock source, offering wide frequency tuning, low power consumption, and enhanced output power. The transmitter employs On-Off Keying (OOK) modulation and delivers a peak output amplitude of$660~ {\mathrm {\text {m}\text {V} }}$with up to 5.1% energy efficiency. At a$20~ {\mathrm {\text {M}\text {Hz} }}$pulse repetition rate, the transmitter consumes only$78~ {\mathrm {\mu \text {W} }}$while producing -24.5dBm of output power. Measurement results confirm compliance with FCC regulations and suitability for deep implantation in biomedical applications. The design achieves a competitive Figure-of-Merit (FoM) of$0.017~({\mathrm {\text {m}\text {m} ^{2}}} \cdot {\mathrm {\text {p}\text {J} }}) / (\text {b} \cdot {\mathrm {\text {V}}})$, demonstrating its scalability and efficiency compared to prior state-of-the-art solutions.

This paper presents an integrated CMOS current driver designed for electrothermal micro-electromechanical-systems (MEMS) switches, fabricated using a 0.18$\mu $m Bipolar-CMOS-DMOS (BCD) process. Unlike conventional constant-voltage drivers typically employed for MEMS actuators with positive temperature coefficient of resistance (TCR), this driver adopts a constant-current actuation. This approach benefits series-connected array components, applications seeking enhanced electromigration control, as well as actuators exhibiting a negative TCR. The system includes a 6-bit programmable digital-to-analog converter, current multiplication circuits, and feedback diagnostic capabilities, enabling precise control and monitoring of actuator performance within a core area of 1.5 mm2. The driver supports pulse-width modulation (PWM) to significantly reduce power consumption compared to DC actuation and implements a double-pulse strategy for accelerating switch activation times. Diagnostic circuits measure actuator resistance within ± 0.5$\boldsymbol {\Omega }$and switching states to enhance reliability in safety-critical applications. Experimental validation confirmed that the driver successfully provides currents up to 110 mA with a resolution of 1.65 mA. At a minimum output voltage of 1.7 V, it can power electrothermal actuators with up to 775 mW under an 8 V supply voltage, corresponding to a power density of 517 mW/mm2. The driver was demonstrated to successfully actuate a chevron-style MEMS switch in 3.5 ms and maintain contact with a 76.7 mA, 50 % PWM waveform at 1 kHz, reducing power consumption by 30.72 %.

An increase in temperature and pressure can cause spontaneous ignition of the air-fuel mixture in internal combustion engines, reducing engine efficiency, lifespan, and increasing air pollution. Typically, to predict and detect this effect, a knock sensor is used, which has a low detection accuracy due to the engine vibration noise. In this work, a machine learning model based on a meta-classifier is proposed and implemented for real-time fault detection in combustion engines. First, actual knock sensor data are recorded at diverse engine speeds from our engine test bench. The local dataset is preprocessed and scaled. Then, 30 different features in the time and frequency domains are investigated. Dimensionality of data is reduced employing recursive feature elimination. Then, a stacking classifier is utilized to address the classification problem by combining several classification models through the use of a metaclassifier. To enhance the assessment of the experimental outcomes in knock detection, k-fold cross-validation is utilized to gauge the model's performance with new data. The result shows the proposed method has around 12% higher accuracy during 5 cross folds with least amount of variation. Finally, the model is implemented on an ARM MCU and showed an execution time of 8.9ms, which validates its reliability for real-time operation.

A switched constant current driver for a configurable switch network based on electrothermal micro-electromechanical-systems (MEMS) components is presented. A constant current-mode approach is proposed for achieving precise power control over an array of devices that leverage thermal heaters for actuation. This multi-channel actuation circuit is able to power different electrothermal MEMS switches. Interface circuits based on the self-temperature sensing technique of the heater and the ohmic contact property of the actuator are proposed. They provide early detection to address MEMS lifetime concerns, and constitute the main novelty of this research, which is specifically focused on the application. The circuit is implemented in a 0.18 μm BCD technology and occupies an area of 1.3 mm2. Post-layout simulations show that the system can output current up to 90 mA (Rheater= 80 Ω) with a resolution of 2 mA.

A deep neural network architecture for the automatic sizing of analog circuit components is proposed, with a focus on radio frequency (RF) applications in the 2 to 5 GHz region. It addresses the challenges of the typically small number of examples for network training and the existence of multiple solutions, of which impractical values for integrated circuit implementation. We address these issues by restricting the learning to one component size at a time, thanks to a cascade of dedicated shallow neural networks (SNN), where each network constrains the prediction of the next ones. Moreover, the SNNs are individually tuned by a genetic algorithm for the prediction order and accuracy. This reduction of the solution space at each step allows the use of small training sets, and the introduced constraints between SNNs handle component interdependencies. The method is successfully validated on three different types of RF microcircuits: a low-noise amplifier (LNA), a voltage-controlled oscillator (VCO), and a mixer, using 180 nm and 130 nm CMOS implementations. All the predictions were within 5 % of the true values, both at the component and performance levels, and all the responses were obtained in less than 5 s, after 4 to 47 min. training on a regular PC station. The obtained results show that the proposed method is fast and applicable to arbitrary analog circuit topologies, with no need to retrain the developed neural network for each new set of desired circuit performances.

This Special Issue is a selection of the best papers presented at the 20th IEEE International NEWCAS Conference (NEWCAS) 2022, which was held in Quebec City, Canada, on June 19–22, 2022. As an interregional flagship conference of the IEEE Circuits and Systems Society (CASS), this conference covers a wide spectrum of topics, research, and practices in the fields of circuits and systems and offers an international forum for exchanging ideas and results.

This paper presents a non-coherent assisted synchronization mechanism for low data rate coherent impulse radio ultra-wide band (IRUWB) receivers. A two-step coarse and fine acquisition mechanism is utilized to simplify the coherent synchronization and minimize the total required packet length. This hybrid scheme reduces the total power consumption of the receiver. The reception of a UWB packet begins with an energy efficient non-coherent synchronization portion in on-off keying (OOK) modulation non-coherent acquisition. This reduces the search space for the coherent reception by first finding the best integration window that has the most energy of the received signal. Afterwards, the receiver searches coherently in binary phase-shift keying (BPSK) modulation within only the pre-selected integration window instead of the whole symbol time. Self-mixing and template-based correlation are utilized for the non-coherent and coherent reception, respectively. Most of the front-end blocks are shared between the coherent and non-coherent modes, including the LNA, mixer, and the baseband circuitry that follows to minimize the total power consumption of the receiver. A differential architecture including a low noise amplifier (LNA), a mixer, a fast start-up template generator, an integrator, and a differential comparator are utilized for the receiver front-end. A prototype of the proposed receiver operating from 3.5 to 5 GHz over four bands, each spaced by 500 MHz, is implemented in 65-nm CMOS technology. The proposed receiver architecture achieves a −68 dBm, −70.5 dBm, and −70.8 dBm sensitivity at a 10−3BER at 50 MHz pulse repetition frequency (PRF) in the non-coherent, coherent, and proposed hybrid synchronization modes, respectively. The receiver consumes 6.8 mW and 8.8 mW in the non-coherent and coherent mode, respectively, when continuously ON. Using its novel synchronization mechanism, the receiver can reduce the ON time of the receiver by 68% and 34% in order to coherently synchronize and receive a 100-bit and 1024-bit payload, respectively. As a result, the energy per useful bit (EPUB) of the receiver is reduced by a factor of 2.9 from 1.24 nJ/b to 422 pJ/b for 100-bit payloads, and by a factor of 1.5 from 309 pJ/b to 204 pJ/b for 1024-bit payloads, increasing energy efficiency while maintaining the sensitivity benefits of coherent detection.

This article presents a multiband low-power and low-complexity impulse radio ultrawideband (IR-UWB) noncoherent receiver. The proposed receiver can be digitally reconfigured in three different modes of operation, including two single-band modes and one concurrent dual-band mode. In the two single-band modes, the proposed envelope detection architecture is capable of receiving and demodulating an ON–OFF keying (OOK) pulse stream at RF center frequencies of 2.8 or 4.8 GHz. In the concurrent dual-band mode, the proposed architecture is able to demodulate binary frequency-shift keying (FSK), in addition to OOK demodulation, at center frequencies of 3 and 5 GHz. The receiver is composed of a reconfigurable low-power differential low noise amplifier (LNA), a fully differential squarer (self-mixer circuit), low-pass filter (LPF), and variable gain baseband (BB) amplifiers. The receiver is fabricated in TSMC 130-nm CMOS process technology. The receiver can operate at up to 150 Mb/s with the ternary signaling that is enabled by the binary FSK modulation combined with the OOK modulation in concurrent dual-band mode. At its maximum gain, the receiver achieves a sensitivity of −72 dBm at a bit error rate (BER) of$10^{-3}$at a 100-Mb/s data rate. It consumes 11.9 and 13.2 mW from a 1.2-V supply in the single-band modes and concurrent dual-band mode, respectively.

A blocker-tolerant harmonic selection receiver front-end with RF bandwidth of 6.5 GHz to support the fifth-generation (5G) sub-6 GHz band is presented. The proposed N-path switching filter-based receiver employs harmonic recombination blocks at the baseband (BB) to select the desired local oscillator (LO) harmonics and suppress blockers. It is demonstrated how the configuration of two feed-forward N-path switching filters and BB harmonic recombination stage can be reconfigured to select the first harmonic of the switching frequency at the low-frequency band (0.5–1.9 GHz) and the third LO harmonic at the high-frequency band (1.95–6 GHz). Thus, the proposed architecture has the capability of supporting an RF input frequency of up to 6 GHz while the switching frequency operates up to 2 GHz. Higher harmonic selection in addition to the fundamental helps to reduce the power consumption and required input frequency of the multiphase LO clock generator. An RF receiver prototype is fabricated in a TSMC 130-nm CMOS technology. It achieves a 5 dB noise figure (NF), −16.6 dBm in-band input-referred third-order intercept point (IIP3), and 9 dBm out-of-band (OOB) IIP3, respectively, at the low-frequency band (0.5–1.9 GHz). The 2nd–5th harmonic rejection ratios (HRRs) are higher than 44 dB without any calibration. The receiver can tolerate a 0 dBm blocker at a 180 MHz offset from a 1 GHz switching frequency with an NF of 9.4 dB. Over the high-frequency band (1.95–6 GHz), the receiver’s NF is less than 7.1 dB. Moreover, in-band IIP3, OOB IIP3, and first HRR are higher than −21 dBm, 7 dBm, and 39 dB, respectively. The receiver achieves an S11 better than −10 dB over 0.5–6 GHz, and has a total power consumption of 17–22.5 mW from a 1.2 V supply.

$N$-path switching systems using switched-series R-C networks are analyzed in the context of RF receiver front-ends, and it is shown that it is possible to mitigate the need to generate an accurate low power clock at high frequencies by operating at higher order harmonics of the switching frequency. For values of$N$that are an integer factor of 4 (i.e.,$N$= 4, 8, and 16), harmonic selection RF receivers’ architectures are presented using two feed-forward$N$-path switching filters and harmonic recombination at the baseband. Moreover, it is demonstrated how the harmonic recombination stage at the baseband can be reconfigured to select the third harmonic of the switching frequency rather than the fundamental to reduce the input frequency and power consumption of the multi-phase clock generator by a factor of 3. In addition, to analyze the performance of the proposed RF receiver architecture, multiple receivers have been designed and post-layout simulated in two CMOS technologies, TSMC 130 nm and TSMC 65 nm. The resulting 5.7–7.2-GHz RF receiver architectures allow for operation at the third harmonic of the LO frequency (i.e., 1.9–2.4 GHz), reducing power consumption and allowing for good performance metrics at both studied technology nodes.

This article describes a design for a frequency synthesizer architecture based on a phase-locked loop (PLL) for avionic software-defined radio (SDR) applications at up to 9 GHz. Three basic architectural schemes: wide range voltage-controlled oscillator (VCO), single sideband (SSB) mixing, and multiple VCOs can be used to extend the frequency ranges. This article compares these schemes through quantitative evaluation to select the best synthesizer architecture to use according to the application specs. The chosen scheme is an optimized combination of a single VCO and a single SSB mixer. Using a quadrature VCO (QVCO) with a switched capacitor (SC) bank, the synthesizer provides a wide frequency band of operation ranging from 100 MHz to 9 GHz covering several avionic communication applications and several existing wireless standards’ frequency requirements. The proposed QVCO is able to generate in-phase and quadrature-phase signals spread into a frequency band between 6 and 9 GHz providing a tuning range of 40% at a center frequency of 7.5 GHz. The QVCO exhibits a phase noise of −107 dBc/Hz, at a 1-MHz offset frequency, while generating a 8-GHz carrier frequency. Its power consumption is of 3.4 mW. With a loop bandwidth of 120 kHz, the frequency synthesizer generates a phase noise, measured at 8 GHz, of −106.4 dBc/Hz at a 1-MHz frequency offset. The overall power consumption of the synthesizer to generate a 140-MHz carrier frequency is 26.57 mW from a 1.2-V supply. The frequency synthesizer is implemented in 0.13-$\mu \text{m}$CMOS technology and occupies an active area of$0.72 \times 0.72$mm2.

This article describes a high-speed optoelectronic receiver implemented in 65 nm CMOS technology. The receiver utilizes only two clock phases instead of the four conventionally used in a quarter-rate clocking system. This two-clock phase system is enabled by a passive silicon photonic split and delay structure that eliminates the need for a quadrature clock phase generator and all the associated buffers. Moreover, the outputs of the receiver are demultiplexed which further helps reducing power consumption in the digital part of the system. The receiver also employs inter-stage AC coupling and is mounted on a high-speed printed circuit board (PCB). The impact of AC coupling and PCB parasitics is investigated. The functionality of the receiver is validated by highspeed optical measurements. The receiver achieves an error-free transmission (BER-12) up to a data rate of 12.5 Gb/s with an energy efficiency of 1.93 pJ/bit and sensitivity of -4 dBm from a 1 V supply.

A low-complexity analog technique to suppress the local oscillator (LO) harmonics in software-defined radios is presented. Accurate mathematical analyses show that an effective attenuation of the LO harmonics is achieved by modulating the transconductance of the low-noise transconductance amplifier (LNTA) with a raised-cosine signal. This modulation is performed through the bias network of a cascode device with a negligible increase in the LNTA noise figure. The proposed technique results in a notch at the third harmonic and at least 36 dB of attenuation at the fifth and the seventh harmonics. Experimental results in 130-nm CMOS and postlayout simulation results in 65-nm CMOS verify the proper functionality of the proposed technique and the accuracy of the proposed analyses.

A gated ring oscillator (GRO) based multi-stage noise-shaping ΔΣ modulator (ΔΣM) is presented in this paper. Loop-filter integrators followed by a digitally implemented GRO make the proposed architecture suitable for scaling-friendly implementations. Quantization noise of the first stage is represented in the time domain and it eases the quantization error extraction with a simple digital circuitry. The GRO offers inherent dynamic element matching, and hence no extra circuitry is needed to linearize the DACs in the feedback path. Time-domain behavioral simulations are shown to study of main GRO non-idealities considering a discrete-time MASH 3-1 topology, featuring a SNDR of 94 dB for an OSR of 16 over a 2-MHz signal bandwidth.

In this paper, a fully integrated frequency synthesizer architecture, designed in 0.13 μm CMOS technology, for avionic software defined radio (SDR) applications is presented. The synthesizer provides a carrier frequency range from 100 MHz to 12 GHz covering the avionic communication applications and existing wireless standards. The switched capacitors voltage controlled oscillator (VCO) used realizes a wide tuning range from 8 GHz to 12 GHz. The VCO phase noise simulated at 12 GHz is −125 dBc/Hz at a 10 MHz offset frequency with a power consumption of 1.4 mW. The transient phase locked loop (PLL) response shows a settling time of 3.92 μs whereas the PLL loop bandwidth is of about 600 kHz. Furthermore, the synthesizer exhibits a phase noise, simulated at 12 GHz, of −104 dBc/Hz at a 1 MHz frequency offset with an overall power consumption of 14.88 mW, comparing favourable to other documented schemes, but with four time the frequency range.

This paper presents a 13-bit fully-differential successive approximation register analog-to-digital converter with a hybrid DAC that is suitable for sensor applications. An innovative dithering plus averaging technique is developed around this originally-designed 10-bit ADC to make it possible to attain an effective resolution of 13 bits in a configurable fashion without calibration. The ADC has a nominal 13-bit sampling rate of 5.5 kS/s suitable for many sensor applications. It operates with a multiple supply voltage from 0.9 V to 0.6V.

An eight-stage reconfigurable charge pump for microelectromechanical system (MEMS) electrostatic actuation was designed and fabricated in a standard 0.13-μm CMOS technology. The purpose of the circuit is to generate sufficient on-chip voltages that are continually reconfigurable for MEMS actuation. Small 1-pF pumping capacitors are used to reduce the circuit area. Digitally programmable voltage levels can be out putted by varying the number of stages and the clock drive levels dynamically. Reduced power consumption is achieved using a variable frequency clock. The circuit attains a measured maximum output voltage of 10.1 V from a 1.2 V supply. Its nominal clock is set to 50 MHz. The circuit has a compact area of 215 μm × 300 μm and consumes 864 μW at a 50-MHz clock and 252 μW at an 8-MHz clock.

A fully integrated current sensing interface chip employing a capacitive-feedback transimpedance amplifier (TIA) is presented. A robust dc current removal block is proposed to prevent the dc portion of the input current from saturating the output voltage. This block allows the TIA to operate in the presence of a wide range of input dc currents, and the cancellation loop is designed to enhance its stability. The TIA is fully integrated in a standard 0.13 μm CMOS technology, and a gain of 170 dBΩ is achieved without requiring any off-chip resistors. The integrated input-referred current noise of the interface circuit is 0.4, 3.8, and 52 pARMS within 0.01, 0.1, and 1 MHz integration bandwidths, respectively.

A 31 stages high voltage reconfigurable charge pump is presented for electrostatic actuation of an optical laterally rotating MEMS mirror. A maximum output voltage of 360.5 V with a rise time of 16.7 ms for a clock frequency of 62.5 kHz is demonstrated through simulations. A variable amplitude clock generator is implemented within the same circuit to control the voltage levels of the charge pump. The maximal output ripple is 1.1 V for a 10 pF load, representing a small relative deviation of 0.31% suitable for MEMS electrostatic actuation. The average step between two consecutive output voltages is 4.9 V between 50 V and 340 V. This small increment enables the fine tuning of the MEMS rotation angle. The circuit is designed in a 0.8 μm high voltage CMOS technology and has an area of 675 μm × 1100 μm.

This paper presents a simple integrated reference based adaptive matching network capable of undertaking real time antenna tuning for applications such as wearable wireless sensors. The signal sent to the antenna is compared to a reference signal using a single flip-flop acting as a phase detector. In case of an impedance mismatch, a counter controlling a capacitor bank is activated reducing the sensed mismatch. The system is capable of three modes: calibration, matching and operation. The calibration mode ensures that the reference signal is in phase with the signal sent to the antenna when the impedance of the antenna is 50 Ω. In matching mode, the capacitor bank is adjusted to maintain antenna matching. In operation mode, the circuit is shut off allowing for low power consumption (85 nW while matching every 1 ms). The circuit is able to provide a VSWR <; 2 over a wide range of antenna impedance levels. It is designed in CMOS 0.13 μm technology.

We describe a method for circuit synthesis that determines the parameter values by using a set of artificial neural networks (ANNs) that learn in sequence. Each ANN is optimized to output only one design parameter, and the latter constrains the learning/recall of its successor(s). Two competing ANN architectures are considered, the multilayer perceptron (MLP) and the radial basis functions (RBF) network, and each one has its internal parameters tuned by a genetic algorithm. The method was tested on the design of a radio-frequency, low-noise amplifier (RF-LNA) with ten design parameters to set, and it yielded one-hundred percent success rate in specifying the parameter values at five percent tolerance.

The successive-approximation-register (SAR) analog-to-digital converter (ADC) has recently attracted a lot of interest due to its power efficiency as well as its simple structure. The main challenge with this type of ADC is the limited sampling rate which is due to its sequential operation. In flash-SAR architectures, this problem is mitigated by cascading flash and SAR ADCs which operate in two consecutive phases. This paper presents a flash-SAR architecture which noticeably increases the ADC sampling rate using pipelined operation of the first-stage flash ADC and the second-stage SAR ADC. In the first stage, a low-power flash ADC is developed using charge distribution dynamic comparators which require no external reference generator. Using the proposed technique, an 8-bit ADC was designed in a 0.13 μm CMOS technology and its simulation results show an SNDR of 49.29 dB with 690 μW total power consumption at 200 MS/s and 1-V supply.

Two techniques to improve the performance of continuous-time delta-sigma (CTDS) modulators are presented. A digital calibration technique is introduced to enable the use of binary current digital-to-analog converters (DACs) without dynamic element matching. Furthermore, a high-speed two-step analog-to-digital data converter quantizer is introduced to efficiently increase the resolution of the quantizer in CTDS modulators with high-sampling rates. A proof-of-concept prototype implemented in 130-nm CMOS shows that the proposed calibration technique can compensate for up to 5% of mismatch in the DAC elements. The modulator has a measured SNDR/SFDR of 60.3/74 dB for a sampling rate of 350 MS/s and oversampling ratio of 20, translating to an 8.75-MHz bandwidth. The total power consumption is 5.5 mW from a 1.6 V supply.

This paper presents an ultra low voltage (ULV), ultra low power (ULP) and ultra wideband CMOS low noise amplifier with noise cancelling. A design methodology for optimizing the trade-off between power consumption and RF performance for a MOS transistor is employed. A current-reuse technique is used to lower the power consumption, and an inductive gm-boosting technique is exploited to increase the gain and improve input matching at high frequencies. The circuit is implemented in a 90nm TSMC CMOS technology. Simulation results demonstrate a 15dB gain, a 6.8GHz bandwidth and a 4.5-5.3dB noise figure. The power consumption is only 410μW at a 0.4V supply.

The preliminary work on a new methodology to design low noise amplifiers (LNAs) for use in radiofrequency (RF) wireless systems is presented. The methodology aims to find the relevant design parameters faster than current analytical models and optimization procedures. To reach this goal, an artificial neural network (ANN) is used to learn the design task by being exposed to successful design examples. Our preliminary results, using a training set of two hundred design examples, show that a radial basis functions ANN can learn the provided designs perfectly, but a larger training set is required for definite conclusions regarding the prediction of component values for new designs.

An on-off keying impulse radio ultra-wideband transmitter with frequency tuning ability based on a 0.13 μm CMOS process is presented. The output spectrum frequency and bandwidth can be adjusted using a digitally programmable oscillator in the 3.7 to 9 GHz range. This allows for the dynamic adjustment of the output spectrum to the surrounding environment. A fully integrated power cycling scheme is used to reduce significantly the power consumption. The transmitter achieves data rates of 10 Mbps with a simulated power consumption of 1.5 mW.

This paper presents a reconfigurable 0.18 μm CMOS ultra-wideband transmitter which supports three modulation schemes: transmitted reference binary phase shift keying, binary phase shift keying and on-off keying. The circuit features three controllable glitch generators combined with a digitally reconfigurable pulse adder which provides the desired output modulation. The transmitter achieves data rates of 100 Mbps with a maximum simulated power usage of 672 μW, while respecting the FCC radiated emissions limits. The transmitted reference allows for a detector to use a straightforward self-correlating mechanism, thus simplifying the required receiver architecture.

This paper presents a MEMS resonator-based vacuum sensor with a low-power transimpedance amplifier and a mixer-based frequency-to-digital converter. The MEMS resonator is fabricated in a CMOS-compatible process, and a 130 nm CMOS technology is used to design the integrated circuitry. The vacuum sensor operates in the pressure range from 10 to 1200 mbar with a resolution of ~2 mbar. The system is temperature-compensated between -10°C and 60°C. The simulated power consumption of the entire system is less than 495 μW from a 1 V supply.

A micro electromechanical beam resonator model that accounts for electrostatic and mechanical non-linearities is proposed. Simulation results are shown to be well matched to fabricated device measurements, capturing non-linear effects such as resonant frequency shifting and the Duffing behavior. Simulations of a MEM resonator-based electronic oscillator using the proposed model show phase noise characteristics which are not predicted by linear models. This offers valuable insights in the trade-offs involved in the design optimization of these oscillators, especially when combined with automatic gain control mechanisms.

Wireless ad-hoc networks are gaining interest for medical, sensing, wearable computing and other applications. The industry is at a critical juncture now where the maturity of RF CMOS can enable these networks. All of these applications, if deployed successfully, results in the proliferation of wireless devices like we have never seen before. The end result is that these devices need to be very low cost, which fits in well with the CMOS paradigm. The challenge going forward is how to make CMOS RF circuits that consume ultra-low power in a compact form factor.