This work presents a Bayesian neural network (BNN) processor for real-time, edge-based medical applications, designed to generate high-volume inference outputs efficiently, providing rapid and precise uncertainty estimation. To address the computational and memory-intensive demands of BNNs, we propose a structured Monte Carlo (MC) dropout method and an efficient processing technique for depth-wise separable convolution, thereby minimizing both the memory and computational burdens. The proposed processor, implemented in 28-nm LP CMOS, is benchmarked on a 12-lead ECG dataset and demonstrates significant improvements in energy efficiency, achieving a$12.9\times $enhancement over conventional MC dropout methods. Furthermore, the processor incorporates a model-switching technique based on uncertainty estimation, resulting in$3.2\times $lower energy consumption while maintaining robust and accurate ECG classification, even under challenging conditions involving noise and motion artifacts.

Split capacitor digital-to-analog converters (split-CDACs) are a promising method to reduce area but face challenges with parasitic sensitivity in high-resolution settings for successive approximation register analog-to-digital converters (SAR ADCs) design. This article introduces a split-CDAC design for improving area efficiency for higher bit resolution by reducing parasitic sensitivity and mismatch. A fundamental reason for the increased parasitic sensitivity stems from the fractional sizing of the bridge capacitor and a small redundant capacitor at the split node. The proposed split-CDAC uses a unit capacitor-based bridge capacitor and a proportionally scaled large redundant unit capacitor, which minimizes these effects to a large extent while achieving linearity. It achieves six times better parasitic sensitivity than a conventional split-CDAC by using six-unit capacitors as a bridge capacitor and 12 times better area efficiency than the conventional binary-weighted CDAC. The proposed fully common-centroided and shielded unit capacitor array, implemented in a 65 nm CMOS process, effectively reduces parasitic and mismatch sensitivity using a simple layout structure. The implementation achieves an INL of less than 1.2 LSB, measured across 21 chips, without mismatch calibration and opens new possibilities for high-precision applications across diverse domains.

Recent research in electronic design automation (EDA) tools has focused on utilizing artificial intelligence (AI) for sizing analog circuit designs. Still, there has been a lack of focus on optimizing complex analog circuits. To optimize complex analog circuits within a few circuit simulations, we propose a partition-and-conquest-based optimizer (PC-Opt). PC-Opt assigns distinct actor-critic roles within a multi-agent system, facilitating the partitioning of complex analog circuits and conquering their optimization challenges. Partial differential training is developed for the proper prediction of each actor, which merges each other and then predicts the optimized entire circuit. To generate a compact and non-biased dataset for network training, a concentrated sampling method is devised. Experimental results on three circuits demonstrate the effectiveness of PC-Opt.

We propose a Diffusion-Enhanced Graph Transformer (DEGT) for analog circuit optimization that overcomes the limitations of traditional vector- and graph-based approaches. Conventional methods struggle to capture the complex connectivity of analog circuits and often require expert-imposed heuristic constraints on the sizing of some transistors to greatly reduce the searching space. In contrast, our method introduces three key innovations. First, an enhanced graph representation combined with a transformer architecture conveys circuit information to the machine learning network without any loss, enabling effective incremental knowledge transfer across various circuit designs. Second, the proposed DEGT quantifies the influence of each device by considering connection distances and path configurations, thereby providing a comprehensive, topology-aware representation of device interactions. Third, a violation handling method autonomously trains non-functional regions in the design space, eliminating the need for expert-imposed constraints or circuit classifications. Experimental evaluations demonstrate that the proposed optimizer consistently improves the figure of merit for a circuit with each round of incremental knowledge transfer using data from different circuits. These results highlight the potential of our approach to advance autonomous analog circuit design by reducing the reliance on expert intervention and improving overall optimization performance.

This paper presents a cryo-CMOS readout SoC based on a homodyne demodulation architecture with an integrating receiver. The homodyne receiver module for each qubit employs a dedicated local LO generator for a coherent detection under a frequency-division multiplexed multi-qubit readout environment. To mitigate the conventional issues of the homodyne demodulation in wireless communications, such as 1/f noise and DC offset by LO leakage, the proposed receiver incorporates effective calibration schemes by utilizing the specific operating conditions of the superconducting qubits. The implemented chip in 40 nm CMOS is tested at 4 K in a dilution refrigerator under an emulated SNR environment of superconducting qubit readout, i.e. -70 dBm input with a noise floor of -148 dBm/Hz. Measurement shows that circuit-only fidelity reaches 99% in 200 ns with an ideal single tone RF input. A back-to-back test using an on-chip 4-tone transmitter shows a 93 % circuit-only fidelity with 400 ns integration.

This brief presents a nano-watt wake-up timer implemented mainly through digital synthesis. By performing successive subharmonic frequency locks between two leakage-based digitally controlled oscillators (DCOs) and repeatedly switching their roles, the period of the timer can be locked to a scaled RC time, enabling low-frequency generation without the need for substantial RC values. The proposed frequency-lock scheme is applied to design a 360 Hz timer. The implemented timer in a 0.18-$\mu $m CMOS process consumes 9.6 nW and shows a standard deviation of 1.36% without the need for extensive external trimming, mainly due to intra-wafer process variation. The measured supply and temperature sensitivities are 0.32%/V and 395 ppm/°C, respectively.

Finding an optimal point in the design space of analog circuits requires a substantial time-consuming effort even for skillful circuit designers. There have been extensive studies on automated sizing of transistors in analog circuits based on machine learning (ML) algorithms. However, the previous approaches suffer from lack of expandability and necessitate an inevitable retraining process of the given model to apply for optimization of different circuits. The graph-based representation of a circuit with reinforcement learning (RL) achieved a knowledge transfer when optimizing the same circuit with different process technologies. However, it can be hardly applied to different circuit topologies due to the failure of generalizing the training of RL agent. This paper introduces Trans-Net, an analog circuit optimizer that is capable of supporting the knowledge transfer across different circuits as well as different process technologies with a circuit representation that defines the circuit topology by one-to-one mapping from SPICE netlist. The proposed analog circuit optimizer successfully supports multiple circuits within a single ML model, showcasing its effectiveness on five different circuit topologies across three different process technologies.

Graph Convolutional Networks (GCNs) have demonstrated their efficacy in various real-world applications such as social networks and recommendation systems. Accelerating GCNs presents unique challenges due to their large number of nodes, sparse and heavily skewed connections. The reordering of the adjacency matrix has been the main strategy to effectively reduce the amount of re-access. Existing techniques of the reordering are categorized into i) degree-based sorting to identify high-degree nodes so that their data could be stored in the cache and ii) graph partitioning to maximally reuse the clustered data. However, as connections among the nodes vary significantly, processing various GCNs with a single strategy would cause performance degradation. This paper presents a software/hardware co-optimized platform for processing of general GCNs. We propose a hybrid scheme in the graph reordering that combines a sorting and a clustering in an adaptively optimized two-way partitioning. The two-way partitioning enables an efficient allocation of the on-chip cache memory space to reduce off-chip memory access by 4-to-12 %. The implemented accelerator in 28nm demonstrates full functionalities with improved energy-efficiency by$2.2-\text{to}-3.7\times$compared to the previous GCN accelerators.

State-of-the-art compact models such as MobileNets and EfficientNets are structured using a linear bottleneck and inverted residuals. Hardware architecture using a single dataflow strategy fails to balance the required memory bandwidth with the given computational resources. This work presents a heterogeneous dual-core accelerator that performs a block-wise pipelined process as a unit using a bottleneck-stationary (BS) dataflow. The BS greatly relieves the requirement on DRAM bandwidth and on-chip SRAM capacity. A look-behind-only attention is also proposed as a co-optimized algorithm. Compared to the state-of-the-art hardware scheme, the proposed accelerator demonstrates a reduction of 1.8-$2.9\times $in latency and 2.2-$3\times $in energy consumption, respectively.For verification, the accelerator with a 16-bit integer precision was implemented using 28nm CMOS process. Measurements show energy efficiencies of 0.5-to-3.75 TOPS/W in a supply voltage range of 0.55-to-1.15V.

This paper presents a physically unclonable function (PUF) based on a ring oscillator (RO) collapse with an improved robustness against temperature variations. To effectively minimize the chances of having temperature-sensitive dark bits, the PUF equips a low-drop-out (LDO) regulator that enables a selection of the supply voltage for each PUF cell, so that uncertainties by temperature change can be minimized whereas those by process mismatch are kept to be large. A reconfigurable RO is also proposed for the PUF cell to effectively transform its shape to have a larger process mismatch. An implementation of the proposed PUF in a 40 nm CMOS shows a bit error rate (BER) of 0.039% in the nominal conditions (0.9 V, 25 °C). The worst-case BER with 0.9 V-to-1.4 V supply and −40 °C -to-125 °C temperature changes is 0.297%. As an indicator of the amount of stability for each PUF cell, the cycles to collapse (CTC) at the nominal conditions is used for the dark bit detection and prescreening. The prescreening reduces the worst-case BER to 0.0092% with 5% masking, to 0.00016% with 10% masking and to zero-error (BER$< 4.88\times 10^{-8}$in the whole 2048 cells over 10K evaluations) with 14% masking.

This brief presents a hybrid oscillator architecture that combines an$LC$resonator and an inverter-based ring oscillator to exploit the inherent benefit of an$LC$resonator for frequency accuracy with low power consumption. This architecture uses the period of the$LC$resonator as a reference time to control the period of the ring oscillator through a feedback loop. By intermittently turning on the$LC$resonator for the period error detection, its power consumption could be reduced to a reasonable level while benefitting from its frequency accuracy over environmental variations. The implemented oscillator in a 40-nm CMOS process achieves a temperature sensitivity of 7.65 ppm/°C in a temperature range of −20 °C–80 °C after two-point batch calibration with a second-order polynomial. A period jitter shows 2.44 psrms with an output frequency of 98 MHz.

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This paper presents an efficient qubit-mapping method that redesigns a quantum circuit to overcome the limitations of qubit connectivity. We propose a recursive graph-isomorphism search to generate the scalable initial mapping. In the main mapping, we use an adaptive look-ahead window search to resolve the connectivity constraint within a short runtime. Compared with the state-of-the-art method [15], our proposed method reduced the number of additional gates by 23% on average and the runtime by 68% for the three largest benchmark circuits. Furthermore, our method improved circuit stability by reducing the circuit depth and thus can be a step forward towards fault tolerance.

In response to the rapid development of quantum processors, quantum software must be advanced by considering the actual hardware limitations. Among the various design automation problems in quantum computing, qubit allocation modifies the input circuit to match the hardware topology constraints. In this work, we present an effective heuristic approach for qubit allocation that considers not only the hardware topology but also other constraints for near-fault-tolerant quantum computing (near-FTQC). We propose a practical methodology to find an effective initial mapping to reduce both the number of gates and circuit latency. We then perform dynamic scheduling to maximize the number of gates executed in parallel in the main mapping phase. Our experimental results with a Surface-17 processor confirmed a substantial reduction in the number of gates, latency, and runtime by 58%, 28%, and 99%, respectively, compared with the previous method [18]. Moreover, our mapping method is scalable and has a linear time complexity with respect to the number of gates.

This brief proposes a resistor-less bandgap reference (BGR) based on a leakage-based proportional-to-absolute-temperature (PTAT) scheme. The effect of process variations on the current is mitigated by employing self-biased current-limiting MOS transistors. The bias voltages needed for approximating a large resistance can be obtained from a single branch by placing threshold-sampling transistors on top of the BGR output. The fabricated BGR in 0.18-$\mu \text{m}$CMOS occupies an active area of 0.035 mm2and consumes 20.5 nW, and it shows a standard deviation of 0.68% at untrimmed reference voltages.

This article proposes a circuit architecture and design strategy of a low-noise oscillator based on the distributedRCnetwork. The distributedRCnetwork receives a differential step input and propagates the true phase through the resistive path while the complementary phase through the capacitive path. It effectively suppresses the effect of noise by increasing the signal transition slope at the time of interest. It is achieved by embedding a bandpass characteristic with a phase delay of$\pi $. A 358-kHz quadrature oscillator with a fourth-stageRCnetwork is implemented using the 0.18-$\mu \text{m}$CMOS process. It achieves an figure of merit (FoM) of −161.2 dBc/Hz at a 100-Hz offset with a stable 20-dB roll-off in the phase noise and an Allan deviation floor of less than 0.7 ppm.

For the first time, we prove that 7.8-Gb/s single-ended signaling through a highly reflective channel is feasible at low energy cost by an energy-efficient many-tap decision feedback equalization (DFE) receiver (RX). The reported data rate of 7.8 Gb/s is the fastest data rate that has been achieved through a single-ended highly reflective channel that has more than five taps of postcursor reflective intersymbol interference. Compared with the prior arts, the target multidrop has the most in-band notches: ten notches. To compensate for large reflection by many notches, the RX exploits the DFE with the largest tap count of 20 that has been never used in single-ended signaling before. Low-power circuit techniques such as a current-integrating summer and double-tail sense amplifiers were adequately adopted and engineered to reduce large power dissipation by many taps. The RX was fabricated in a 65-nm CMOS technology and occupies only 0.014 mm2. The energy efficiency was measured to be only 2.9 pJ/b at 7.8 Gb/s with 0.9-V supply, proving that fast single-ended signaling through a highly reflective channel is feasible at low energy cost by many-tap DFE if low-power circuit techniques are adequately applied. The horizontal and vertical eye sizes were measured to be 0.12 UI and 34 mV, respectively, at a bit error rate of-12.

This paper presents a sub-10 nW bandgap reference (BGR) circuit that implements both voltage and current references in one circuit. The BGR circuit was implemented with a 0.18μm CMOS process and generates voltage and current references of 1.238 V and 6.64 nA while consuming 9.3 nW. The voltage and current references show standard deviations of 0.43 % and 1.19 % with temperature coefficients of 26 ppm/°C and 283 ppm/°C, respectively.

This paper presents a body-channel communication (BCC) transceiver adopted with decision feedback equalization (DFE). The proposed transceiver, fabricated in 65-nm CMOS process, achieves reliable (BER-6) data rates of 150 Mb/s (16.6 pJ/b), and 100 Mb/s (23.5 pJ/b) over 20-cm and 1.3-m channels on human limbs. The transceiver occupies a total core area of 5580 qm2, which is less than 1% compared to any previously-presented work.

This paper presents an amplifier-less and digital-intensive current-to-digital converter for biosensors. The proposed circuit achieves a first-order noise shaping of the quantization error without any continuous-time feedback circuit. Also, it minimizes static power consumption by employing a single-ended current-steering digital-to-analog converter (DAC) which flows only the same current as the input. The effect of dynamic switching noise become input-independent constant by adopting switching averaging algorithm. The implemented circuit in 0.35pm CMOS converts an input range of 2.8pA to 15b digital output in about 4ms, while consuming 16.8pW.

In this paper, we propose a search algorithm to find the worst operation scenario of a cross-point array of a phase-change random access memory to enable a precise read margin evaluation. The search algorithm utilizes a particle swarm optimization method to find the worst scenario quickly and efficiently. In an experiment, the proposed algorithm improves the search speed by 39.3× compared with the previous algorithm. With the improved search speed, the proposed algorithm could find the worst operation scenarios of large arrays whose worst operation scenarios had been only guessed before. In the experiment with a large array, the proposed algorithm proved that the worst high-resistance state read current can be 36× larger than the previous best guess. In the reliability test, the evaluation error of the worst read current found by the proposed algorithm is less than 0.2% with 99% probability. These results show that the proposed search algorithm can improve the precision and efficiency of the read margin evaluation in designing a cross-point phase-change memory array.

An all-synthesizable current-mode transmitter driver for a USB2.0 high-speed (480 Mb/s) interface was proposed to enhance the design portability. The proposed driver was implemented using tristate inverter cells. It uses the differential current-mode architecture, with variable output voltage swing, and includes a predriver. It was also successfully applied to the 480-Mb/s USB2.0 TX driver with the synthesized serializer and phase-locked loop.

This paper disproves the worst read scenario of a ReRAM crossbar array. If the previously believed worst read scenario is not the worst one, the read margin evaluated based on the scenario can be incorrect. We explored for read scenario worse than the previously believed worst scenario by wisely sampling scenarios and iteratively searching for the worse one. In experiment, our algorithm successfully found the scenario worse than the previously believed one, disproving the previously believed worst read scenario. Our results show that the sensing window estimated by the incorrect previously believed worst scenario is 14 times as large as the estimation by the worst scenario found by our algorithm.

A Gm-based amplifier is proposed for the use in low-voltage and low-power switched-capacitor circuits. At the input stage of the amplifier, a common-mode current-suppression scheme effectively suppresses the common-mode current with the differential-mode current even amplified, resulting in decrease in dc power consumption. At the output stage of the amplifier, a self-biased cascode configuration adaptively changes bias voltages to achieve both the cascode operation for high gain and digital switching operation for fast transients. The proposed amplifier is applied to a design of an 11-bit pipelined ADC with a 0.13-$\mu \text{m}$CMOS process. The implemented analog-to-digital converter consumes 80$\mu \text{W}$from a single 0.7 V supply at 2.5 MS/s. It achieves an effective number of bit of 9.72 bit without any calibration scheme and a figure of merit of 37.8 fJ/c-s at near Nyquist rate.

This paper proposes a technique to reduce the sample number of channel's pulse response required to optimize equalization coefficients. In our method, channel's pulse response is aliased in calculating equalization coefficients reducing the number of samples of the channel's frequency response. As a result, the computation time to acquire the channel's frequency response is greatly reduced. To demonstrate our method, equalization coefficients are calculated using the conventional and our methods and then compared. Since the necessary number of samples is reduced by 8 times at most in our method, the computation time is reduced up to by 7.01 times. For accuracy verification, we also calculated the equalized eye sizes using both methods. The calculated eye sizes are almost identical. These results show that using our method, engineers can accurately optimize equalizing transceiver design with reduced efforts to simulate channel's frequency response.

The time-periodic property of the LCD VCOM noise is utilized to reduce the effect of the VCOM noise on the mutual-capacitance measuring touch sensor placed on a LCD panel. The amplitude of the touch sensor driving signal (VSTM) can be reduced reliably down to 0.4 V with the reporting rate of 189 Hz, by using the following two methods. (1) The frequency of VSTM is set to (n+0.5)·fN, by synchronizing VSTM to a LCD gate driver signal with a referenceless CDR. fN is the inverse of the LCD VCOM noise period (TN) and n is a positive integer. (2) The reset period of the RX integrator is set to 2·TN.

This paper describes the characteristics of a half-rate clock-embedded source-synchronous signaling scheme to identify its constraints and to optimize the transceiver topology in the presence of a band-limited channel. The proposed signaling combines the half-rate clock to the common mode of the differential data with its mixing phase off by 0.5 UI. Two transceivers with resistive-load and inductive-load receivers are implemented in 130-nm CMOS technology to verify their feasibility for use as serial links. The prototype transceivers achieve a wide operating frequency range 2.25-6 and 5.6-8 Gb/s, respectively, satisfying bit error rate of-12measured at Tx-Rx linked configuration by 5-in-long FR4 trace with 231-1 PRBS. The power efficiencies of transceivers at maximum data rates are 6.4 and 4.6 mW/Gb/s, respectively.