As a forefront core functional module, a bootstrapped sampling switch (BSS) built-in an analog-digital converter (ADC) contributes to realize a high-precision signal sampling in bioelectrical sensing systems. A novel algorithm-based automatic approach to guide the optimal design of a high-performance bootstrapped sampling switch is proposed. Within the first manual topology optimization, a complementary sampling transfer-gate is designed to suppress the clock feed-through effect, and a dynamic body bias control module and an improved bootstrapped closed-loop-path are constructed to effectively improve the linearity. In the secondary core algorithm-based performance solving stage, a support vector regression (SVR) machine is adopted to further explore the best design tradeoff between dynamic noise feature and power dissipation according to the model-training-based optimal solution of the design parameters. SMIC 180 nm/1.8 V standard CMOS technology is employed to implement the front/back-end design of the proposed BSS circuit, and pre-/post-layout simulations for feature verification are performed. Final experimental results show that, targeting a test benchmark signal of 100 Hz and 1.2 V p-p in 51.2 kHz sampling frequency, after mixed-optimization-based ENOB and SNR can be reached up to 12.969 bits and 103.046 dB, respectively. Similar to the other two key dynamic performance indexes, SFDR and THD are also improved to 70.905 dBc and -69.508 dB, respectively. In the design case comparison, with a higher power supply voltage of 1.8 V and kHz-order frequency, the average power consumption is only approximately 0.188 μW. These feature results demonstrated the significant effectiveness of the proposed SVR algorithm aided artificial optimization approach on bootstrapped sampling switch design, and the comprehensive specification of switches can meet the demand of the specific application of highly accurate human bioelectrical signal sampling.

Two 1 novel automatic generation methods for analog layout—a symmetrical twin-row method for MOS transistors and a twisted common-centroid method for capacitor arrays—are introduced. Based on the proposed layout styles and the corresponding algorithms, the symmetry and common-centroid placement patterns for analog devices are realized to guarantee matching properties. On this basis, as the most prominent contribution of this article, channel routing-based algorithms for the proposed layout styles are presented and could achieve 100% routability due to well-arranged devices and corresponding low routing complexity. The algorithms benefits include a small layout area that maximizes the diffusion-sharing of MOS transistors and less routing layer usage for common-centroid device arrays. Moreover, we successfully applied our algorithms to the layout designs of two typical analog modules including a two-stage operating amplifier and a Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). The generated layouts and the circuit simulation results demonstrate the effectiveness of our algorithms in terms of their routability and matching properties. Our algorithms can also be extended to apply to a variety of essential MOS analog circuits.

This paper presents a low supply voltage design of stochastic flash ADC, introducing an inverter-based comparative unit which is used as the front-end. A stochastic flash ADC has a significant advantage in reducing the supply voltage, while it needs a large number of comparators even for middle-level resolution. A key of our design is in the simplicity of the structure, and it enables us to decrease the number of transistors by replacing a comparator with a chain of inverters. Plus, the supply voltage can go down to 0.6V on 65nm process, as well as it can be designed with fully digital standard cells. We introduce a latch circuit combining with the chain of inverters for the signal stability, and discuss about an appropriate circuit structure for the resolution by analyzing three different structures. In the simulation, we demonstrate fundamental but promising results for a low voltage ADC design.

For analog circuits, the current source is one of the most essential functions, and variation of its characteristic seriously influences to the accuracy of the performance. This paper presents a new methodology for analyzing the layout dependency of the variation of the current source transistor. We employ a current-driven D-A converter to investigate the dependency of the current source upon the relative accuracy and the ¿. We implemented the D-A converts with various layout structures into TEG(Test Element Group), and evaluated them. The analysis convinced us that the diffusion sharing and gate folding significantly influence to the variation of ¿ and relative accuracy.