Spiking neural networks (SNNs) can improve inference accuracy through joint optimization of synaptic weights and neuronal thresholds. However, mixed-signal neuromorphic processors, which are designed for energy efficiency using analog circuits, face practical limitations. In particular, digital to analog converters (DACs) often lack sufficient resolution to represent the large threshold values required by joint optimization. To address this issue, we propose a mixed-signal neuromorphic processor architecture that shifts threshold control to digital logic. This approach removes the need for high-resolution DACs and allows dynamic threshold adjustment without modifying the analog neural core. We also propose a learning method tailored to this architecture. We evaluate the proposed design on five image classification benchmarks, measuring accuracy, latency, and energy consumption. The results show that our architecture consistently improves accuracy across benchmarks while incurring only minimal latency and energy overhead. This demonstrates that the proven benefits of joint weight and threshold learning can be realized in energy efficient analog hardware.

Neuromorphic Processor eXpress (NPX) is a framework designed to facilitate the development of lightweight neuromorphic processors. To evaluate its efficacy, we conducted a case study involving the FPGA-based implementation of a traffic sign recognition system using an NPX-generated neuromorphic processor. The prototype integrates camera input and OLED output, successfully demonstrating full functionality. This case study confirms that NPX substantially streamlines the design and deployment of efficient neuromorphic processors for embedded artificial intelligence applications.

Neuromorphic inference applications primarily rely on general matrix-matrix multiplication (GEMM) and twodimensional convolution (Conv2D) operations. When conventional artificial neural network (ANN) acceleration techniques are employed, these computations often necessitate extensive data reordering, which imposes significant overheads, especially in lightweight embedded systems with limited CPU and memory bandwidth. To address this challenge, we propose a unified accelerator architecture executing GEMM and Conv2D operations without data reordering. The accelerator is co-designed with a neuromorphic software framework tailored for lightweight embedded systems. To validate effectiveness, we implement a neuromorphic processor incorporating the proposed accelerator on an FPGA. Evaluation results across four representative neuromorphic applications demonstrate that the proposed design reduces execution time and energy consumption by 69% and 89%, respectively, compared to conventional ANN accelerators.

Developing low-power neuromorphic processors capable of inferring outcomes from SNN Frameworks presents significant challenges, largely due to the gap between frameworks and analog circuit-based SNNs. This paper analyzes the root of this gap as stemming from over/underflow issues and proposes mixed-signal neurons as a solution, further developing a neural core composed of these neurons. In the development of the neural core, we incorporate a design methodology for application-specific neural core optimization. We advance to develop a neural engine as an independent IP, ultimately introducing the snnTorch Architecture (STARC), an integrated mixed-signal neuromorphic processor architecture. The STARC processor, developed as a prototype, demonstrates operational correctness and exceptional low-power performance.

As applications running on lightweight RISC-V processors become increasingly diverse and complex, the need for multicore processors supporting floating-point units (FPUs) is riseing, making processor designs using existing open-source RISC-V cores challenging. With the exception of a very few, most open lightweight RISC-V cores are integer cores without FPUs, which greatly reduces the design exploration space, making it impossible to design a processor optimized for each application. For example, most of these applications mainly perform integer operations, but occasionally perform floating-point operations. For them, a multicore processor with FPU per core is overkill and wastes power, which is a critical problem for processors where low-power design is paramount. To address the problem, we propose an external lightweight FPU that can be attached to any RISC-V integer core and a low-power multicore architecture using the designed FPU. For verification, we designed a RISC-V processor that implements all the proposed technologies, prototyped it on an FPGA device, and finally fabricated it as a System-on-Chip. Through experiments, it was confirmed that the proposed technology can cut energy consumption energy by up to 23%.

With the growing interest in robot related research and industry, there is a demand to shape user experience more sophisticatedly in human-robot interaction. The purpose of this study is to define the elements for manipulating robot's verbal anthropomorphism and investigate the influence on user experience associated with spatial context. Based on the identified elements, we divided the robot's anthropomorphism into three levels (high, medium, low) and associated them with two spatial contexts (open, closed). The results revealed that a higher level of verbal anthropomorphism mostly induced positive user experiences; however, people sometimes tended to prefer a medium level, especially in terms of usefulness. Further, privacy concerns were significantly higher in open space. Consequently, we propose that designers and researchers deviate from the two levels of anthropomorphism (e.g., high or low, existing or not) generally used in prior studies to a new perspective that also considers the spatial context.

Ranging from circuit-level characterization to designing a platform architecture, developing a design automation tool, and fabricating a System on Chip (SoC), this article deals with the entire development process for ultralow-power (ULP) SoCs for Internet-of-Things (IoT) end nodes. More precisely, this article first focuses on the unique characteristics of the ULP circuits, the temperature effect inversion (TEI), i.e., the delay of the ULP circuits decreases with increasing temperature. Existing TEI-aware low-power (TEI-LP) techniques have incredible potential to further reduce the power consumption of conventional ULP SoCs, but there is a critical limitation to be widely adopted in real SoCs. To address this limitation and realize the ULP SoCs that can fully benefit from the TEI-LP techniques, this article proposes a new TEI-inspired SoC platform (TIP) architecture. On top of that, taking into account that the highly complex, time consuming, and labor-intensive development process of these ULP SoCs may hinder their widespread use for IoT end nodes, this article presents a new electronic design automation tool to accelerate ULP SoC development, RISC-V express (RVX). Finally, by using the RVX, this article introduces a TIP prototyping chip fabricated in 28-nm FD-SOI technology. This chip demonstrates that power savings of up to 35% can be achieved by lowering the supply voltage from 0.54 to 0.48 V at 25 °C and 0.44 V at 80 °C while continuing to operate at a target 50-MHz clock frequency.

Researchers have been trying to exploit the temperature effect inversion (TEI) phenomenon to improve energy efficiency of system-on-chip (SoC) designs without sacrificing its performance. However, TEI-aware low power methods have a critical limitation in that they can only be applied to components within the SoC that do not contain long (global) wires. This is because wire delays continue to increase with rising temperatures irrespective of the operating supply voltage level, which tends to cancel out positive effects of the TEI phenomenon in SoCs. To tackle this limitation and thoroughly utilize the TEI-aware methods, this paper presents new TEI-inspired SoC platform (called TIP), which relies on network-on-chip architecture (called μNoC) to realize system interconnects. The μNoC successfully reduces the total number and length of global wires. By fabricating a TIP prototyping chip in Samsung 28nm FD-SOI technology, we verify the effectiveness of TIP. Extensive post-fabrication measurements demonstrate that the chip while continuing to operate at a target 50MHz clock frequency can lower its supply voltage from 0.54V to 0.48V at 25°C and to 0.44V at 80°C, which results in up to 35% power saving.

XML-enabled publish-subscribe (pub-sub) systems have emerged as an increasingly important tool for e-commerce and Internet applications. In a typical pub-sub system, subscribed users specify their interests in a profile expressed in the XPath language. Each new data content is then matched against the user profiles so that the content is delivered only to the interested subscribers. As the number of subscribed users and their profiles can grow very large, the scalability of the service is critical to the success of pub-sub systems. In this article, we propose a novel scalable filtering system called iFiST that transforms user profiles of a twig pattern expressed in XPath into sequences using the Prüfer's method. Consequently, instead of breaking a twig pattern into multiple linear paths and matching them separately, FiST performs holistic matching of twig patterns with each incoming document in a bottom-up fashion. FiST organizes the sequences into a dynamic hash-based index for efficient filtering, and exploits the commonality among user profiles to enable shared processing during the filtering phase. We demonstrate that the holistic matching approach reduces filtering cost and memory consumption, thereby improving the scalability of FiST.

Web services composition search systems have received a great deal of attention recently. However, current solutions have limitations of inefficiency and including redundant Web services in the results. In this paper, we proposed a redundant-free Web services composition search based on a two phase algorithm. In the forward phase, the candidate composition will be found efficiently by searching the link Index. In the backward phase, redundant-free Web services compositions are generated from the candidate composition by using the concepts of tokens. Experimental results demonstrate the performance benefits of our proposed techniques compared to state-of-the-art composition approaches.

Web services search and discovery systems have received a great deal of attention recently. However, little attention has been given to a Web services filtering system. In this paper, we propose a design and architecture of a semantic Web services filtering system called SWFilter. SWFilter uses Prufer sequences transformed from Web services and user queries. The filtering process is performed in a bottom-up manner. Ontology information and compositions of Web services are also considered in the filtering process.

In recent years, the Web services composition has received much attention. By Web services composition, we mean taking advantage of currently existing Web services to provide a new service that does not exist on the repository. In this paper, we propose a new system called PSR for Web services composition search using a relational database. We also propose algorithms for pre-computing Web services composition using joins and indices. We demonstrated that our pre-computing Web services composition approach in RDBMS yields lower execution time and good scalability when handling a large number of Web services and user queries.

A spatial distance join is a relatively new type of operation introduced for spatial and multimedia database applications. Additional requirements for ranking and stopping cardinality are often combined with the spatial distance join in online query processing or Internet search environments. These requirements pose new challenges as well as opportunities for more efficient processing of spatial distance join queries. In this paper, we first present an efficient k-distance join algorithm that uses spatial indexes such as R-trees. Bidirectional node expansion and plane-sweeping techniques are used for fast pruning of distant pairs, and the plane-sweeping is further optimized by novel strategies for selecting a sweeping axis and direction. Furthermore, we propose adaptive multistage algorithms for k-distance join and incremental distance join operations. Our performance study shows that the proposed adaptive multistage algorithms outperform previous work by up to an order of magnitude for both k-distance, join and incremental distance join queries, under various operational conditions.

With the rapid advances of wireless communications and positioning techniques, tracking the positions of moving objects is becoming increasingly feasible and necessary. Traditional spatial index structures are not suitable for storing these positions because of numerous update operations. To reduce the number of update operations, many existing approaches use a linear function to describe the movements of objects. In many real applications, however, the movements of objects are too complicated to be represented as a simple linear function. In this case, such approaches based on a linear function cannot reduce update cost efficiently. In this paper we propose a novel R-tree based indexing technique called LUR-tree. This technique updates the structure of the index only when an object moves out of the corresponding MBR (minimum bounding rectangle). If a new position of an object is in the MBR, it changes only the position of the object in the leaf node. It can update the position of the object quickly and reduce update cost greatly. Since it is based on the R-tree, the LUR-tree also uses the same algorithms to process various types of queries as the R-tree. We present the experimental results which show that our technique outperforms other techniques.

A spatial distance join is a relatively new type of operation introduced for spatial and multimedia database applications. Additional requirements for ranking and stopping cardinality are often combined with the spatial distance join in on-line query processing or internet search environments. These requirements pose new challenges as well as opportunities for more efficient processing of spatial distance join queries. In this paper, we first present an efficient k-distance join algorithm that uses spatial indexes such as R-trees. Bi-directional node expansion and plane-sweeping techniques are used for fast pruning of distant pairs, and the plane-sweeping is further optimized by novel strategies for selecting a sweeping axis and direction. Furthermore, we propose adaptive multi-stage algorithms for k-distance join and incremental distance join operations. Our performance study shows that the proposed adaptive multi-stage algorithms outperform previous work by up to an order of magnitude for both k-distance join and incremental distance join queries, under various operational conditions.

SOPView is a graphical user environment for SOP OODBMS. SOPView supports the frame-based visual specification of object-oriented database query elements such as target classes, projections, conditional predicates, and path expressions. SOPView also provides a browsing method which consists of components such as visualization structure, synchronized browsing, and intermediate reference set query in order for users to understand and access the complex reference hierarchy in object-oriented databases with ease.

An essential function of the multimedia DBMS is to present objects of the query result according to their temporal-spatial relations. These relations can be specified within the database schema on the class level and used for each object presentation. In the case of partial extraction, however, the retrieved objects may not belong to an existing class, but to a newly created class which does not have temporal-spatial relations. For the presentation of such objects, most systems make users perform authoring of the temporal-spatial relations of the objects. The paper proposes a scheme which generates presentation schedules for the query result whether the objects of the query result belong to existing classes or not. In this scheme, a TS-tree (temporal/spatial tree) is defined as the temporal-spatial structure of a class and the presentation schedules for objects of the class are generated from the tree. The TS-tree for objects which belong to a newly created class can be automatically generated from existing TS-trees. Consequently users are quite relieved from authoring efforts.

It is true that some conventional algorithms do not fit in continuous media (CM) environments because of their different properties. A typical example is the buffer replacement algorithms such as least recently used (LRU) and most recently used (MRU) strategies. These replacement policies are based on the referencing history for replacing buffered page with lower priority because it is not always possible to predict when a buffered page will be re-referred in a traditional DBMS. In contrast, since a CM storage system accesses CM segments sequentially, it can replace buffered segments which will not be re-referred in the near future. The idea of a far-future-using (FFU) buffer replacement algorithm is to share the buffer for concurrent transactions and to keep segments in the order of a re-referencing plan. We analyze the FFU buffer replacement algorithm for CM playback in terms of buffer hit ratio and required buffer size in comparison with LRU and MRU.

Previous works on buffer management in the database area paid little attention to the dynamic buffer allocation involving reallocation of buffers of queries while exploiting the known access patterns of the database operations. This paper proposes a new buffer allocation technique to improve the system's global performance. The main idea is to maximize the effectiveness of the buffer allocation. For this end, the less-utilized buffers of queries are partially preempted and reallocated to the other queries which can utilize them more effectively. The proposed technique reduces the waiting time portion of query processing through the flexible buffer allocation. The simulation results show that the proposed technique performs better than the conventional ones.

Forward traversal methods are used to process queries having nested predicates in object-oriented databases. To expedite the forward traversal, a signature replication technique is proposed. Object signature is a signature formed by values of all atomic attributes defined in the object. When an object refers to other objects through its attribute, the object signature of the referred object is stored into the referring object. Using object signatures, nested predicates can be checked without inspecting referred objects.>

A relational database workload analyzer (REDWAR) is developed to characterize the workload in a DB2 environment. This is applied to study a production DB2 system where a structured query language (SQL) trace for a two-hour interval and an image copy of the database catalog were obtained. The results of the workload study are summarized. The structure and complexity of SQL statements, the makeup and run-time behavior of transactions/queries, and the composition of relations and views are discussed. The results obtained provide the important information needed to build a benchmark workload to evaluate the alternative design tradeoffs of database systems.>

The object-oriented data model has gained popularity in developing database systems for new applications which include AI, CAD, and OIS. In modeling such applications, it is necessary to capture not only data semantics but also knowledge semantics, such as constraints and deductive rules. The authors describe an approach to data/knowledge modeling which combines various modeling features of the object-oriented data model with deductive capabilities of the deductive database system.>