This work addresses the problem of automating the electrical optimization of combinatorial MOS circuits. Improvements to a circuit's speed, area and power consumption are sought through modifications to the transistor sizes in the circuit; no changes in the circuit structure, number of gates or clocking are introduced. Linear algorithms are presented for computing optimal transistor sizes to minimize delay, area or power. These algorithms are implemented in an interactive tool, Aesop. Aesop is a powerful and fast “what-if” tool that allows the designer to explore the space of designs having optimal transistor sizes. When compared to manual designs, the circuits produced by Aesop are typically faster or have substantially lower area and power consumption. Compared to untuned circuits, Aesop typically increases circuit speed by a factor of 2 to 4. Alternatively, power consumption and transistor area can be reduced by 25 — 50% with no sacrifice in circuit speed. These improvements are computed interactively on a professional workstation for circuits containing thousands of transistors.

This tutorial is an introduction to performance modeling in the design of integrated circuits (ICs). It assumes no background in either electrical engineering or VLSI design; all relevant concepts and terminology will be introduced. The goal is to give an overview of the role of performance modeling in IC design, the current state of the art, central problems and research challenges.

This work addresses the problem of improving an nMOS PLA's speed and power consumption through modifications to the transistor sizes in the PLA. A simplified model of gate delay (lumped RC model) is used that allows rapid estimation of delays thus allowing interactive computation of optimal transistor sizes. Algorithms are presented for: a) minimization of delay through the PLA b) minimization of power consumption subject to a bound on maximum delay. Both these minima are computed subject to bounds on the transistor sizes. A prototype electrical optimization tool was compared to the PLA generation tools in the Berkeley CAD tools package (eqntott and tpla). The maximum delay through a PLA can often be reduced by a factor of 2, and power consumption along the critical paths can be reduced by 10 - 30% without increasing maximum delay.