The rapid reduction in critical dimension of integrated circuits has lead to substantial mask data expansion for mask design based on traditional model-based full-chip optical proximity correction (OPC). Conventional EPE-OPC is mainly based on edge placement error (EPE) without consideration of its effect on circuit performance; often resulting in an overcorrected OPC mask with little improvement in circuit performance at the expense of much higher cost. In this paper, a performance-based OPC (PB-OPC) methodology is proposed taking into account both performance and cost. A less complex mask is generated based on the performance matching criteria. The framework exploits thein situestimated postlithography performance deviation error to drive the customized mask design algorithm. In particular, device PB-OPC (DPB-OPC) was deployed to systematically synthesize both polysilicon and diffusion masks by using mean drive current deviation as the controlled performance index. The proposed approach is validated via detailed simulation using 65-nm foundry libraries and IEEE International Symposium on Circuits and Systems 1985 (ISCAS'85) benchmark circuits. When compared to conventional performance-aware EPE-OPC approach, the proposed DPB-OPC achieved 34% average reduction in mask size and up to 13.5% reduction in mean drive current deviation within reasonable run time.

Along the continued shrinking of critical dimension (CD), the optical proximity correction (OPC) scheme inevitably becomes more aggressive and results in greater mask complexity and cost. Conventional OPC are edge-placement-error (EPE) driven without considering the effect of correction on circuit performance at all. We propose a performance-based OPC (PB- OPC) framework that employs a much simpler mask correction algorithm based on the real-time estimated device performances. When compared to the conventional OPC approach, our PB-OPC achieved 33 to 93% reduction in mask MEBES size and closer circuit performance matching to the design intent.