With the latest advances in technology scaling, reliability of IC design has emerged as an issue of significant concern in the VLSI design community. Reliability is a global concept that needs to be challenged with a system-level approach: all disciplines in circuit and systems education are steadily introducing reliability aspects in their coursework. Still, engineers need to be educated to a holistic view that must include in one context all different aspects of a digital system (analog / digital / packaging / board / software). This work describes an attempt at increasing the coverage and efficacy of this specific learning outcome in digital design courses, introducing a new tool and a new set of lab assignments on top of “standard” digital design flows introduced in previous offerings.

Recently, system designers are facing the challenge of developing systems that have diverse features, are more complex and more powerful, with less power consumption and reduced time to market. These contradictory constraints have forced technology providers to pursue design solutions that will allow design teams to meet the above design targets. In that respect, this paper introduces an innovative technology platform, called MORPHEUS, which intents to provide complete design framework for dealing with the aforementioned challenges. MORPHEUS consists of a state of the art architecture that encompasses heterogeneous reconfigurable accelerators for implementing on the same hardware architecture applications with varying characteristics and a tool chain that, through a software oriented approach, eases the implementation of highly complex applications with heterogeneous characteristics. The proposed approach has been tested and evaluated through state of the art cases studies borrowed from complementary application domains.

This paper describes the application space exploration of a heterogeneous digital signal processor with dynamic reconfiguration capabilities. The device is built around three reconfigurable engines featuring different flavours and computation granularities that make it suitable for a wide range of signal processing application domains such as video coding, image processing, telecommunications, and cryptography. Performance of signal processing applications is evaluated from measurements performed on a CMOS 90 nm prototype. In order to characterize the application space of the processor, performance is compared with state-of-the-art devices, taking programmability, computational capabilities, and energy efficiency as the main metrics. The device exploits performance and energy efficiency significantly more than general purpose processors, while still maintaining a user-friendly programming approach that mainly relies on software-oriented languages. The device is able to achieve 1.2 to 15 GOPS with an energy efficiency from 2 to 50 GOPS/W when running the selected applications.

Reconfigurable architectures and NoC (Network-on-Chip) have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting run-time adaptivity opens a new area of research by considering dynamic reconfiguration. In this paper, we present the architecture and associated development tools of an heterogeneous reconfigurable SoC focusing on the chosen communication infrastructure. The SOC integrates units of various sizes of reconfiguration granularity. The included NoC approach demonstrates the mentioned benefits and scalability for actual and future SoC design. On a reference CMOS090 implementation the described interconnect system works at the system reference frequency of 200 MHZ sustaining the required run-time bandwidth on a set of reference applications, at a price ≪ 10% in area in power consumption with respect to the overall system.

Linear feedback shift registers (LFSRs) are common structures in many application fields, including cryptography, digital broadcasting and communication. High- throughput requirements need highly parallel implementations, usually accomplished in state of the art system on chips (SoCs) with application specific coprocessors. Although this approach achieves the required performance, it rapidly shows lack of flexibility when those devices are proposed, as an example, for multi-standard modems or for security applications in which run-time update can provide added value. This paper shows the implementation of parallel LFSR-based applications on an embedded adaptive DSP featuring a Pipelined Configurable Gate Array (PiCoGA). With respect to standard embedded FPGAs, pipelined devices usually provide better performance, e.g. in terms of speed, but they commonly show the undeniable drawback of additional design constraints. As a test-case, we consider the implementation of the 32-bit CRC used in the Ethernet standard that achieves on the target architecture up to ~25Gbit/sec throughput, with a parallel LFSR processing 128 bit at time, which is comparable to the performance offered by some ASIC devices.

Many reconfigurable hardware architectures have been proposed so far, ranging from FPGAs to coarse grained architectures. Reconfigurability can be intended in several ways, and a number of diverse solutions have been proposed. One of the most relevant issues that have emerged is that the performance gain offered by reconfigurable hardware is balanced by relevant difficulties in their programming, which often inhibit its utilization in many appealing fields and ultimately jeopardize its diffusion. The solution for enabling higher productivity in application mapping likely do not reside only in the development of better tools, but also of more usable designs. This paper gives an overview of different reconfigurable architectures and related design flows proposed over the last years, including commercial offers and efforts coming from academia, analyzes the challenges they pose to the application developer and focuses on the latest alternatives to mitigate the design productivity issue.

The application of embedded run-time configurable architectures to System-on-chip design has long been considered a possible major enabling factor, especially in the direction of lowering time-to-market of new products as well as mitigating NRE costs related to verification, bug-fixes and product upgrades. In fact, while achieving significant success in specific application fields, reconfigurable computing has so far mostly failed to reach the high-volume application specific standard products (ASSP) that both in terms of volumes and revenues represent the largest share of today's SoC market. This is essentially due to the area overhead induced by these solutions with respect to standard ASIC design styles, which is unaffordable for the low margins that characterize this specific product class. In this paper, the exploitation of mask-programmable hardware technologies for deploying high volume ASSP is evaluated as a possible mitigation factor to the above discussed issues. The paper provides an introduction to mask-programmable technologies as well as an overview and a classification of most significant available trends and solutions in the field. In particular, the application of mask-level programmability in the context of the most significant trends in reconfigurable architectures is thoroughly discussed. In the authors' opinion it is both useful and necessary to capitalize on and exploit the valuable legacy created by 10 years of exploration of reconfigurable architectures in the context of the new possibilities offered by the emergence of mask-programmable options as a significant factor in SoC design.

This paper describes a digital signal processor based on a multi-context, dynamically reconfigurable datapath, suitable for inclusion as an IP-block in complex SoC design projects. The IP was realized in CMOS 090 nm technology. The most relevant features offered by the proposed architecture with respect to state of the art are zero overhead for switching between successive configurations, relevant area and energy computational density on computational kernels (average of 2 GOPS/mm2, 0.2GOPS/mW) and relatively small area occupation (18 mm2), making it suitable for acceleration or upgrade of multi-core heterogeneous embedded platforms. The processor is delivered with a software tool chain providing the application developer algorithmic analysis and design space exploration based on ANSI C, with no utilization of hardware-related constructs or description languages

Reconfigurable architectures provide the user the capability to couple performance typical of hardware design with the flexibility of the software. This paper presents the design of AES/Rijndael on a dynamically reconfigurable architecture. A performance improvement of three order of magnitude was shown compared to the reference code and up to 24times speed-up figure wrt fast C implementations over a RISC processor. A maximum throughput of 546 Mbit/sec is achieved. Compared to prior art, a better energy efficiency with respect to the other programmable solutions was shown, obtaining up to 3 Mbit/sec/mW

This paper presents a local buffer memory in the form of a stream register file (SRF) that was developed in order to connect, in a compiler-friendly pattern, large-bandwidth run-time configurable logic units in processor-based SOCs. The proposed SRF offers to the host SOC system performance speedups in the range of 4times, with area/power overhead in the order of 6%. The described hardware and algorithm mapping strategy was implemented on silicon in a SOC based on the PiCoGA reconfigurable architecture. The SOC provides an average 450 MOPS (mega operations per Second) in STM CMOS090 technology running at 100MHZ

Embedded real-time multimedia applications pose several challenges in order to satisfy increasing quality of service (QoS) and energy consumption constraints, that are hardly matched by the capabilities of general-purpose standard processors. Reconfigurable processors, coupling the flexibility of software-programmable devices with the computational efficiency of application specific architectures, represent an appealing trade-off for next generation devices in the digital signal processing application domain. In this paper, we present a benchmarking application for the XiRisc reconfigurable processor, based on a public release of the MPEG-2 video encoder. The introduction of the reconfigurable logic gives a 5/spl times/ performance improvement and a 66% energy saving.

In this letter, the implementation of a system-on-chip for the documentation of road accidents is presented. Key features of the system are the implementation on a programmable architecture of a compression algorithm capable of encoding up to 20 black and white QCIF frames/s, and the computation of a digital signature performed every frame which is applied to the encoded bitstream certifying the source of the video sequence. The acquired images are then stored on a battery of on-chip flash memories that can be used to retrieve accident information to be used in legal confrontations. Having to perform in critical energy conditions (e.g., continued image acquisition for up to 10-20 s after an accident has occurred), the system was designed to minimize energy consumption at all levels. The system-on-chip has been implemented in 6/spl times/6 mm/sup 2/ on a 0.25-/spl mu/m 6-metal standard-cell CMOS technology and works at 40 MHz with a 2.5-V power supply. Performance can be decreased to 12 QCIF frames/s, 24 MHz, and 1.3-V power supply in order to achieve 30-mW power consumption.

In the field of embedded systems, reconfigurable processors, composed of a standard processor core coupled with a reconfigurable device, are gaining more and more importance. Algorithm developers are facing the issue of mapping applications on configurable hardware, without a specific knowledge of the underlying architecture. In this paper, we present a modular data flow control unit for a reconfigurable datapath, which can be easily programmed starting from the C description of the required functionality.

Multi-context FPGAs are a convenient solution for run-time reconfiguration, but they suffer from large area occupation. This is mainly due to programmable interconnect configuration memories which need to be replicated as many times as the number of contexts. This limitation can be overcome with a DBM (Decoder Based Multicontext) routing architecture which introduces a decoding stage between configuration memories and routing structures, so that the number of SRAM cells can be highly reduced. Both the switch and connect blocks have been designed, at the architectural and schematic level. A suitable router for DBM structures has also been developed. The results show that the approach adopted requires on average only 5% more tracks whereas the device area occupation is reduced up to 40%. We also show that DBM routing architecture does not affect the critical path delay, due to the reduction of the routing wire length.

In recent years the challenge of high performance, low power retargettable embedded system has been faced with different technological and architectural solutions. In this paper we present a new configurable unit explicitly designed to implement additional reconfigurable pipelined datapaths, suitable for the design of reconfigurable processors. A VLIW reconfigurable processor has been implemented on silicon in a standard 0.18 μ m CMOS technology to prove the effectiveness of the proposed unit. Testing on a signal processing algorithms benchmark showed speedups from 4.3x to 13.5x and energy consumption reduction up to 92%.