CypherDB addresses the problem of protecting the confidentiality of database stored externally in a cloud and enabling efficient computation over it to thwart any curious-but-honest cloud computing service provider. It works by encrypting the entire outsourced database and executing queries over the encrypted data using our novel CypherDB secure processor architecture. To optimize computational efficiency, our proposed processor architecture provides tightly-coupled datapaths that avoid information leakage during database access and query execution. Our simulation using a well-known database benchmark TPC-H over a commercial grade Database Management System (SQLite) demonstrates that our proposed architecture incurs an average of about 10 percent overhead when compared with the same set of operations without secure database processing.

Many applications use encryption to protect data confidentiality, which require decryption before any data processing. Integrating ASIC design of encryption engines and general-purpose processor can yield the best overall performance in program execution as it benefits from low latency hardware engine and high processor memory bandwidth. However, ASIC design is fixed once manufactured, which cannot afford any changes in the implemented cryptographic algorithm. FPGA implementation is attractive in terms of its re-configurability but it is generally much slower than ASIC design. In this demo, we present a novel scheme that can offload the latency of reconfigurable cryptographic engine from the overall execution and define an en-/decryption data interface, which is independent of the underlying encryption algorithms. To verify our proposed scheme, we implemented a FPGA prototype, which integrated our design with OpenRISC on ALTERA DE2i-150 evaluation board. We prove that our proposed architecture can flexibly and efficiently en-/decrypt the data with zero overheads towards overall program execution with careful design. Our case study on SQLite shows that the query execution over a 1GB encrypted database on our implemented system introduces performance overhead ranging from 0% to 14%.

A novel method for detecting edges and lines simultaneously and automatically is proposed. This method, based on phase congruency and tensor voting (hence PCTV), makes use of the properties of how edges and lines are built from the Fourier decomposition of an image, and how the primary visual cortex responds to them, instead of making assumptions on the intensity profiles of the regions near a feature. Experiments showed that the detection results were more consistent to the “ground truth” manually drawn by humans. For detecting edges, this method is superior to three commonly used detectors in that it reduces the production of false detections.

Anisotropic diffusion is an iterative process which provides efficient signal smoothing with feature preserving capabilities. However, the traditional anisotropic diffusion algorithms are highly sensitive to the number of iterations. In this paper, we introduce a novel method in the diffusion formulations to stabilize the diffusion results. It is generally applicable to most of the anisotropic diffusion algorithms, and the experimental results show that the stabilized algorithms provide improved results.

This paper proposes a general quadrilateral-based framework for image segmentation, in which quadrilaterals are first constructed from an edge map, where neighboring quadrilaterals with similar features of interest are then merged together to form regions. Under the proposed framework, the quadrilaterals enable the elimination of local variations and unnecessary details for merging from which each segmented region is accurately and completely described by a set of quadrilaterals. To illustrate the effectiveness of the proposed framework, we derived an efficient and high-performance parameterless quadrilateral-based segmentation algorithm from the framework. The proposed algorithm shows that the regions obtained under the framework are segmented into multiple levels of quadrilaterals that accurately represent the regions without severely over or undersegmenting them. When evaluated objectively and subjectively, the proposed algorithm performs better than three other segmentation techniques, namely, seeded region growing, K-means clustering and constrained gravitational clustering, and offers an efficient description of the segmented objects conducive to content-based applications.

Looks at the development of innovation and technology funding, infrastructure and achievements in Hong Kong in the past few years, and examine the potential areas where Hong Kong can excel and be a significant contributor to technology development. Comparison will be drawn from Finland, an economy of a size and GDP very similar to that of Hong Kong.

This paper proposes a novel tracking method based on quadrilateral-based segmentation. The tracking method matches quadrilaterals in a region with those in a reference frame to construct region correspondences, from which trajectory of each region can be obtained. The table tennis sequence has been used to evaluate the tracking method. Experiment results show that the proposed tracking method can track the ping-pong ball and the racket reasonably well over a series of images, indicating matching quadrilaterals to track region is a viable approach.

This paper presents the design and performance of a new parallel graphics renderer for 3D images. This renderer is based on an adaptive supersampling approach that works for time/space-efficient execution on two classes of parallel computers. Our rendering scheme takes subpixel supersamples only along polygon edges. This leads to a significant reduction in rendering time and in buffer memory requirements. Furthermore, we offer a balanced rasterization of all transformed polygons. Experimental results prove these advantages on both a shared-memory SGI multiprocessor server and a Unix cluster of Sun workstations. We reveal performance effects of the new rendering scheme on subpixel resolution, polygon number, scene complexity, and memory requirements. The balanced parallel renderer demonstrates scalable performance with respect to increase in graphic complexity and in machine size. Our parallel renderer outperforms Crow's scheme in benchmark experiments performed. The improvements are made in three fronts: (1) reduction in rendering time, (2) higher efficiency with balanced workload,: and (3) adaptive to available buffer memory size. The balanced renderer can be more cost-effectively embedded within many 3D graphics algorithms, such as those for edge smoothing and 3D visualization. Our parallel renderer is MPI-coded, offering high portability and cross-platform performance. These advantages can greatly improve the QoS in 3D imaging and in real-time interactive graphics.

In this paper, we propose an efficient barrier synchronization scheme on networks with arbitrary topologies. We first present a distributed method in building a barrier routing tree. The barrier messages can be delivered adaptively according to the hierarchy of the established barrier tree to void congestion and faulty nodes in the network. We then propose a new technique, called bandwidth-preempting technique, for a blocked barrier message to preempt a channel occupied by a data message so that the latency of a barrier message can be controlled without affecting much of the overall system performance. We also propose an analytical performance model and present simulation results for the performance evaluation of the proposed scheme. Performance evaluations show that the proposed scheme outperforms the existing algorithms for barrier synchronization.

This paper presents a parallelization methodology for video coding based on the philosophy of hiding as much communications by computation as possible. It models the task/data size, processor cache capacity, and communication contention, through a systematic decomposition and scheduling approach. With the aid of Petri-nets and task graphs for representation and analysis, it employs a triple buffering scheme to enable the functions of frame capture, management, and coding to be performed in parallel. The theoretical speedup analysis indicates that this method offers excellent communication hiding, resulting in system efficiency well above 90%. To prove its practicality, a H.261 video encoder has been implemented on a TMS320C80 system using the method. Its performance was measured, from which the speedup and efficiency figures were calculated. The only difference detected between the theoretical and measured data is the program control overhead that has not been accounted for in the theoretical model. Even with this, the measured speedup of the H.261 is 3.67 and 3.76 on four parallel processors (PPs) for QCIF and 352/spl times/240 video, respectively, which correspond to a frame rate of 30.7 and 9.25 frames per second, and system efficiency of 91.8% and 94%, respectively. This method is particularly efficient for platforms with a small number of parallel processors.

In this paper, we introduce a family of scalable interconnection network topologies, named Recursive Cube of Rings (RCR), which are recursively constructed by adding ring edges to a cube. RCRs possess many desirable topological properties in building scalable parallel machines, such as fixed degree, small diameter, wide bisection width, symmetry, fault tolerance, etc. We first examine the topological properties of RCRs. We then present and analyze a general deadlock-free routing algorithm for RCRs. Using a complete binary tree embedded into an RCR with expansion-cost approximating to one, an efficient broadcast routing algorithm on RCRs is proposed. The upper bound of the number of message passing steps in one broadcast operation on a general RCR is also derived.

This paper presents an attempt towards design quality improvement by incorporating of self-testability features during data path (high-level) synthesis. This method is based on the use of test resource sharing possibilities to improve the self-testability of the circuit. This is achieved by incorporating testability constraints during register assignment. Experimental results are presented to demonstrate the effectiveness of the proposed data path synthesis for BIST approach.

Area and test time are two major overheads encountered during data path synthesis for BIST. This paper presents an attempt towards testability enhancement in data path BIST synthesis by considering two factors simultaneously. It is achieved by incorporating two testability constraints in data path synthesis. Experimental results are presented to demonstrate the effectiveness of the proposed (data path) BIST synthesis approach.

Detection of delay and transistor stuck-open faults requires two-pattern tests. BIST provides a low-cost test solution. This paper exploits the BIST approach for two-pattern testing. The generation of a pseudo-deterministic test-pair sequence with LFSR was exploited. A three-step approach is proposed. First, a set of deterministic test-pair is generated to detect all robust path delay faults. Second, LFSR-based TPG configurations are calculated to have pre-generated test-pair embedded in a set of maximal length pseudo-random test sequences. Third, a global cost-optimal BIST solution for data path (using pseudo-deterministic TPGs) is proposed. The second step is formulated as a cluster-covering problem. The third step is formulated as an 0-1 ILP. Experimental results are presented to demonstrate the effectiveness of the proposed approach.

We describe a parallel rendering method based on the adaptive supersampling technique to produce anti-aliased images with minimal memory consumption. Unlike traditional supersampling methods, this one does not supersample every pixel, but only those edge pixels. We consider various strategies to reduce the memory consumption in order for the method to be applicable in situations where limited or fixed amount of pre-allocated memory is available. This is a very important issue, especially in parallel rendering. We have implemented our algorithm on a parallel machine based on the message passing model. Towards the end of the paper, we present some experimental results on the memory usage and the performance of the method.

This paper presents a new motion estimation algorithm using an adaptive search center predicted from its adjacent blocks, and a non-linear center biased search point pattern. It does not have the problem of being trapped by local minimum, and is characterized by finding the majority motion vector in one step. When compared with six other block-based search algorithms including the full-search and three-step-search, the new algorithm has an average PSNR very close to that of full-search, yet its average search time is faster than the three-step-search.

With respect to scalability and arbitrary topologies of the underlying networks in multiprogramming and multithread environments, fault tolerance in acknowledged ATAB and concurrent communications become a challenge to reliable general wormhole routing multicomputers with arbitrary topologies. In this paper, the virtual ring tree (VRT) is proposed to deal with the challenge. A single startup is needed in the two proposed algorithms by a simple virtual node space, which also reduces the complexity of routing at intermediate steps of ATAB algorithms and re-beginning an ATAB, by cacheable virtual channels. The proposed algorithm can automatically handle static faults in networks.

Block matching algorithms (BMAs) are often employed for motion estimation (ME) in video coding. Most conventional fast BMAs treat the ME problem as an optimization problem and suffer heavily from the problem of being trapped at local minima. The full search algorithm (FS), on the other hand, is very time-consuming. Few of them makes use of the information inherent in the images explicitly. We propose a new ME algorithm which can reduce the search range while guaranteeing global optimality in most cases, making use of the edge features. Microblock visual patterns are designed to extract edge information to guide block matching: searching is only carried out at places where the real match most likely happens. The motion field subsampling technique is further employed to get a hierarchical algorithm, which can further double the speed. The proposed algorithms obtain speeds about ten times faster than that of FS with comparable prediction quality.

To include fuzzy properties in solving some types of problems, the attributes graph is extended to provide a fuzzy-attribute graph (FAG). With such an extension, equality of attributes can no longer be used when matching of FAGs is considered, as equality of two fuzzy sets is too stringent a condition. A measure for matching two FAGs is suggested. The measure has its interpretation in fuzzy logic. The result of applying the model to the recognition of handprinted Chinese characters is presented.>

In everyday life, many properties or concepts we encumber are fuzzy in nature. To include those fuzzy properties in solving some types of problems, we have extended the attributed graph to fuzzy-attribute graph (FAG). With such extension, equality of attributes can no longer be used when matching of FAG's is considered, as equality of two fuzzy sets is too strigent a condition. In the paper, fuzzy-attribute graph is formally defines and a new measure for matching two FAG's is suggested. Yhe new measure has its interpretation under fuzzy logic. The model is applied to the recognition of handprinted Chinese characters and the result is presented.