This paper presents a generalized formulation of the periodic steady-state analysis for oscillators. The new formulation finds the value of a circuit parameter that results in a desired oscillation frequency for the circuit. Numerical methods based on the time-domain finite difference and shooting methods, and the frequency-domain harmonic balance method are described. Comparisons with search-based methods demonstrate the efficacy of the new approach.

In this paper a modification of the time-domain periodic steady-state analysis for oscillators is presented. The proposed analysis finds the value of a circuit parameter that results in the circuit oscillating at a desired frequency. This analysis is based on the steady-state analysis for voltage and current controlled oscillators, i.e., replacing the oscillation period by a circuit parameter in the list of unknowns. A generalized formulation that can handle a control voltage or current, as well as any frequency-tuning circuit parameter, such as a tank capacitor or device geometry is developed in this paper.

This paper introduces the problem of finding the steady-state and the numerical value of the controlling voltage or current for oscillators where the frequency of oscillation is known beforehand. These situations are very common when the oscillator is part of a phase-locked loop (PLL). In PLLs, the reference frequency as well as the divide ratios are known at the time of design. Therefore the desired frequency of the voltage (current) controlled oscillator is known but not the controlling voltage (current). We formulate this problem as the solution of an appropriate nonlinear equation. We present robust and efficient numerical techniques for solving this nonlinear equation both in time and frequency domain. We demonstrate using experimental results that this technique is at par with classical methods of calculating oscillator steady-state and period of oscillation for a given control voltage. We show that compared to a search-based approach to calculating the desired control voltage or current, our direct method is a order of magnitude faster for the same accuracy.

This paper introduces a novel chip shaping scheme increasing the network capacity in DS-CDMA systems without any increase in. bandwidth or chip rate, and without performance degradation. The chip shape corresponds to an interferometry pattern created by the superposition of N carriers. Two sets of orthogonal chip shapes with minimum inter-chip interference are positioned pseudo-orthogonally (in time) within a single symbol duration, allowing the novel system to support many more chips in the same symbol duration and bandwidth. Simulations performed over Rayleigh fading channels indicate the new chip shaping (and corresponding detection strategy) enables 100% gains in DS-CDMA network capacity without any loss in performance. With the exception of chip shape and receiver design, this new system retains all the features of a conventional DS-CDMA system.

This paper proposes a novel maximum likelihood combining (MLC) scheme for MC-CDMA systems. Currently, minimized mean square error combining (MMSEC) is widely considered the best combining scheme for MC-CDMA. The MLC proposed in this paper is optimal from the standpoint of minimizing the probability of error performance. It is shown that MLC is very close to MMSEC in a fully loaded system, justifying the selection of MMSEC over other combining schemes. Moreover, when the load is small (as measured by number of users), MLC is shown to outperform MMSEC (and, other combining schemes).