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Jared Ahrens

dblp:58/4574 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › hardware verification › circuit-level verification
asynchronous circuit verification		 0.112008
A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › hardware verification and test › formal verification
compositional verification		 0.112008
A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › hardware verification and test
hardware verification		 0.112008
A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › logic synthesis › logic optimization
state minimization		 0.112008
A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008

Methods — techniques the papers use, named apart from their topics

state space reduction · 0.1interface refinement · 0.1
YearPublicationVenuePosition
2008 A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification
abstract
This paper presents a compositional method with failure-preserving abstraction for scalable asynchronous design verification. It combines efficient state-space reductions and novel interface refinement and can dramatically reduce the complexity of state space while decreasing the introduction of false failures. This allows much larger designs to be verified as demonstrated in the experimental results.
Hao Zheng 0001, Jared Ahrens
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2