This paper presents a rigorous transfer function analysis of the power supply rejection ratio (PSRR) of low-dropout (LDO) regulators and the LDO with the feed-forward ripple cancellation (FFRC) scheme. Four main noise sources of conventional LDOs are first clarified. An efficient and accurate model is proposed to facilitate the analysis, and the transfer function, along with the poles and zeros, is derived based on the simplified model. Software simulation results and numerical plots are both demonstrated and compared to verify the analytical results, with respect to two specific design examples. The widely-used FFRC scheme for PSRR enhancement is also reinvestigated based on the proposed model. With the inclusion of the FFRC circuit, the new transfer function with new poles and zeros is presented. The working principles of the FFRC scheme are illustrated and the optimal FFRC case is clarified. The proposed model and the derived transfer function match well with the simulation results and the measurement results in prior works. The proposed model and the analytical results serve as the theoretical foundation of the design of high-PSRR LDOs. The recommended simulation methodology could be helpful during the circuit design phase.

This paper presents a gate driver for a GaN-based half-bridge structure operating in a buck converter with input voltage >40 V or a boost converter with output voltage >30 V. Two 500 pF on-chip capacitors are utilized to construct three-level gate drivers, providing a near-$V_{{\text {DD}}}$negative voltage for gate of the rectifier switch to eliminate the induced pulse on the gate from the highdv/dtslew rate of$V_{\text {X}}$when the main switch is turned on. The dead time controller tunes the delay of the gate signal of the rectifier switch by sensing the slope of$V_{\text {X}}$, thus the near-optimal zero-voltage switching can be achieved with deviation$\mu \text{m}$BCD process. The efficiencies can be improved by 8.33% and 6.87% at light load in a buck and a boost converter due to the dead-time control. The peak efficiencies of 20 V–12 V and 12 V–18 V conversions are 86.37% and 84.39%, respectively.

This work presents a 25 MHz adaptive on/off-time-controlled three-level buck converter with a fast reference tracking speed and high light load efficiency. The self-balancing scheme of the flying capacitor voltage is revised and extended for a broad conversion ratio range from 0.17 to 0.833. To reduce the error of the self-balancing scheme when applied to a high frequency three-level buck converter with an on-chip flying capacitor, a real-time calibration loop on the flying capacitor voltage is introduced, effectively reducing the balancing error from 340 mV to 20 mV. A turning-point output voltage prediction for the three-level buck converter is presented to achieve near-optimal reference tracking with a fast tracking speed and negligible output voltage undershoot or overshoot. The up- and down-tracking takes 81 ns and 72 ns, respectively, for a 1-V step with an inductor of 47 nH and an output capacitor of 47 nF. The three-level converter achieves a precise discontinuous conduction mode (DCM) operation with an adaptive switching frequency at light load by means of a feedback loop-based method. An approximately 28.2% increment in efficiency is achieved with a load of 10 mA. The three-level buck converter has a peak efficiency of 92.8% and an over 85% efficiency in most of the operation regions.

This work presents the novel integration of a reconfigurable piezoelectric energy harvester array (RPA) with a parallel synchronized switch harvesting on inductor (P-SSHI) rectifier. The proposed design realizes maximum power point tracking (MPPT) by adjusting RPA with changes in vibration amplitude. Compared with the traditional interface systems based on monolithic piezoelectric energy harvester (PEH), this design can operate in a wider range of input voltage, removing the need for a DC-DC converter, essential in the traditional design. This adaptability eliminates the need for extra-passive components and reduces switching loss. RPA can be also configured in series to reduce the inherent capacitance of PEHs, effectively improving the extraction efficiency of P-SSHI rectifier. Simulations of this system show that the efficiency of the RPA/P-SSHI combined system can be kept above 66% within an input voltage range from 0.03V to 4.39V.

This paper presents a rigorous transfer function analysis of the power supply rejection ratio (PSRR) of typical capacitor-less low-dropout (LDO) regulators. An efficient and accurate model is proposed to relieve the complication. The transfer functions, together with the poles and zeros, are obtained regarding a typical capacitor-less LDO topology as an example. The numerical results are plotted and compared to circuit simulation results using a commercial 65-nm technology for verification, and using the proposed model the mechanisms of different PSRR enhancement techniques are discussed. The proposed model and derived transfer functions match well with the simulation and measurement results in prior works.

A single-inductor Boost and Buck-Boost hybrid converter is proposed for thermoelectric generators (TEG) with a reversal in polarity. A novel topology with optimized parameters significantly reduces the power loss of the converter. Ultra-low-power control circuits make the converter applicable to an input power ranging from hundreds of nanowatts to hundreds of microwatts. The proposed converter is implemented in a 0.13-μm CMOS process. The input voltage range is -300 mV to -10 mV and 10 mV to 300 mV. The power dissipation of control circuits is as low as 24 nA. The peak end-to-end efficiency is 91.5% when the available power is 274 μW. Higher than 70% end-to-end efficiencies can be achieved over a range of available power from 4.3 μW to 429 μW.

A fully integrated single-input dual-output switched-capacitor converter with dynamic power-cell allocation for application processors is presented in this summary. The power cells can be dynamically allocated according to the loads, and the efficiency is improved by 4.8%. A dual-path voltage-control oscillator (VCO) that works independently of the power-cell allocation is proposed to achieve a fast and stable regulation loop. The converter achieved peak efficiency of 83.3% and maximum combined load-currents of 100mA while maintaining minimized cross regulation.

A 5.5W mains-powered converter-free LED driver for general lighting application is presented in this summary for the university design contest. The driver is superior to its switching converter based counterparts as it does not require any bulky and expense magnetics or electrolytic capacitors. In addition, the driver is able to significantly reduce the flicker at light output with a quasi-constant power control scheme. The measurement results show that the prototype driver achieves 88.2% efficiency and 0.92 power factor with only 18% flicker at 110VAC 60Hz input.

In ultrasound image analysis, speckle tracking methods are widely applied to study the elasticity of body tissue. However, “feature-motion decorrelation” still remains as a challenge for speckle tracking methods. Recently, a coupled filtering method was proposed to accurately estimate strain values when the tissue deformation is large. The major drawback of the new method is its high computational complexity. Even the GPU-based program requires a few hours to finish the analysis. In this paper, we propose an FPGA-based implementation for further acceleration. The capability of FPGAs on handling different image processing components in this method is discussed. The algorithm is reformulated to build a highly efficient pipeline on FPGA. The final implementation on a Xilinx Virtex-7 FPGA is 15 times faster than the GPU implementation on two NVIDIA graphic cards (GeForce GTX 580).

A more accurate steady state analysis of the zero-voltage switching quasi-resonant (ZVSQR) converter is conducted in this paper. The conversion ratio equation and the conditions to achieve zero-voltage switching (ZVS) are derived. According to the analysis, a ZVSQR converter can be designed to operate within a wider input voltage range. A ZVSQR inverted buck converter is simulated as an example to verify the analytical results.

A systematic analysis of 3-level integrated buck converters is conducted in this paper. Detailed derivations of the working principles, voltage conversion ratio and output voltage ripple are given. In particular, the system loop gain of 3-level buck converters is analyzed, which provides guidance on designing fast and robust 3-level converters. The derived loop gain is verified with time-domain small signal injection analysis. The results show a good match between analytical and simulation results.

Recent advancement in commercial MEMS-based piezoelectric energy harvesters has enabled further reduction of both system cost and size as the device dimension scales down. A nature inspired interface circuit by mimicking water bucket fountain to harvest piezoelectric charge is presented. The proposed architecture offers built-in input voltage protection, harvests electrical energy using minimal switching activity and does not cause mechanical dampening to the piezoelectric cantilever. System simulation and measurement using a standard CMOS 0.13μm process verified the proposed architecture. The pulse transformer boost converter has self-start voltage as low as 45mV and peak efficiency up to 75%, whereas the remaining digital control and voltage processing circuits require less than 1.5μW to operate.

An output capacitor-less low-dropout regulator (LDR) with enhanced transient responses for system-on-a-chip (SoC) power management applications is presented in this paper. The boosted push-pull driving capability is realized by applying a transient-adaptively-biased folded-cascode error amplifier structure with a cross-coupled output stage that achieves higher dc gain and faster slew rate. The proposed LDR is compensated by combining active feedback (AFC) and adaptively-biased damping-factor-control (DFC) effectively. The idea of the LDR is implemented with a standard 65-nm CMOS process. The on-chip compensation capacitance is only 200fF. The output is 1.0V, which delivers a maximum current of 50mA at 200mV drop-out, and the output capacitor can be as large as 100pF. Extensive simulations verify that the proposed LDR can recover from 100ns-edged 10μA-50mA load transient and 1.2V-1.8V line transient in 200ns, with much reduced over-/under-shoot at the output.

This paper presents the analysis and design of three-state controlled transition mode for buck-boost converter. By introducing an additional state D2to the transition mode, a significant efficiency improvement and output voltage ripple reduction are achieved due to the reduced average inductor current and inductor current ripple. Furthermore, the stability of the converter is enhanced according to the dynamic behavior analysis. A buck-boost converter operating in transition mode has been designed and implemented using AMS 0.35μm CMOS technology. Simulation results demonstrate that over 10% efficiency improvement can be achieved at heavy loading and the converter can be stabilized with a smaller compensation capacitor.

This paper proposes a High-Side (HS) NMOS power switch and bootstrap driver with DCM charging phase extension for high-frequency fully-integrated converters with 1.2V supply voltage. The conventional bootstrap diode is replaced by a self-synchronized switch and the efficiency loss and operation failure at DCM is prevented by an extra charging phase. Simulation at 100MHz with UMC 0.13μm process shows that the optimum efficiency is driven 2% higher with significant power loss reduction by the proposed design compared to a conventional converter under similar operation conditions. 20% power stage area is saved by the dual NMOS structure compared to the conventional converter with PMOS and NMOS switches.

Inductor current information can be used by digitally controlled DC-DC converters as control signal or over-current protection. In most of the existing approaches, the digital inductor current-sensing and quantization are always designed and implemented as two separated functional blocks, e.g. an analog current sensor and an ADC. This is actually a redundant approach and designing a high-gain amplifier in deep sub-micron process is power consuming. Therefore, this paper proposed an on-chip digital inductor current sensor which combines both the sensing and quantization into a single functional block. In this way, chip area and power consumption can be saved. An 8-bit digital inductor current sensor for 4MHz buck converter is designed and implemented. Simulation results show that the sensor has linear and monotonic properties with LSB of 2.7mA.

A 4-transistor (4-T) CMOS voltage reference with two high PSRR output voltages is presented. The output voltages are equal to the scaled voltage difference of two threshold voltages at absolute zero temperature. The temperature coefficients' (TCs) difference of the two threshold voltages is compensated by another transistor-size-controlled temperature coefficient to achieve zero TC outputs. A CMOS voltage reference with 0.5V-1.2V supply voltage, two output voltages of 182mV and 85.5mV, is implemented with a 0.13μm CMOS process. Simulation results show that temperature coefficients of 32ppm/°C and 52.5ppm/°C from 0 to 100 °C, and line sensitivities of 0.095%/V and 0.104 %/V are achieved for the two reference voltages, respectively. The supply current is 3nA under all the supply voltage range at room temperature. Moreover, the power supply rejection ratios (PSRRs) of two outputs are -63.83dB and -70.4dB at 100Hz, and -77dB and -98dB at 100kHz, respectively.

Design optimization methodology of an output capacitor-less low-dropout regulator with small internal compensation capacitance for on-chip application with slew-rate enhancement circuit is presented in this paper. The on-chip compensation capacitance is reduced down to 1.5pF. The idea has been modeled and fabricated in a standard 0.35μm CMOS process. From experimental results, with minimum dropout voltage of 0.2V and 30μA quiescent current, the regulator implemented can operate with supply voltage from 2.4V to 3.3V at maximum loading current of 100mA.

A Single-Inductor-Dual-Output (SIDO) buck converter with Cross-Regulation-Suppression (CRS) control scheme is presented. The converter operates in continuous-conduction-mode (CCM) and employs ordered-power-distributive control (OPDC) to distribute the inductor current to the two outputs. The novel CRS control method is used to suppress the cross-regulation (CR) of the SIDO which is an important issue in OPDC CCM converter design. On-chip type-III compensator is incorporated in the SIDO converter to eliminate off-chip components and accelerate system response. The CRS controlled converter is fabricated with AMS 0.35μm CMOS process and operates at 2MHz. Measurement results show that this converter achieves a cross-regulation down to 0.056mV/mA with 180mA load current changes and a response time less than 20μs. The maximum efficiency is 91.8%.

A novel single-inductor-dual-output (SIDO) boost regulator with hysteretic control to minimize the cross interference and enable a fast transient response is presented. In order to have a predictable system switching noise spectrum, the switching frequency of the converter is synchronized to multiple fraction of a predefined high frequency according to the loads and during transient. A boost converter with 1.8V-2.4V input voltage, two regulated output voltages between 3.0V and 3.6V, each with maximum 500mA driving capability, is implemented with a 0.35μm CMOS process. Simulation results show that the load transient response time is less than 5μs and no noticeable cross-regulation can be observed when load current changes from 10mA to 500mA.

An integrated fixed frequency adaptive-on-time DC-DC converter with fast transient response is presented. To achieve fixed frequency, the slope information of the inductor current is employed to adjust the on-time and keep the switching frequency constant at 1MHz to within 10% variation across the whole input/output and loading ranges. An integrated boost converter with an input voltage of 1.8V to 2.4V and a regulated output voltage between 3.0V and 3.6V was implemented with a 0.35μm CMOS process. Simulation results show that the switching frequency variation has ~40% and ~30% improvement over the traditional input/output voltage controlled adaptive-on-time technique when the load current changes from 0.1A to 0.8A and the inductor ESR changes from 0Ω to 0.2Ω, respectively. The load transient response time is about 20μs when the load current changes from 200mA to 800mA.

A monolithic quasi-fixed-frequency DC-DC boost converter with a modified-adaptive-off-time (MAOF) control is presented. To achieve a quasi-fixed-frequency in whole loading range, the new MAOF control is able to overcome the frequency variation problems naturally exist in traditional adaptive-off-time control in both continuous- and discontinuous-conduction-mode (CCM and DCM) operations. The MAOF control boost converter was implemented with a 0.35μm High Voltage (HV) CMOS process. With 3V - 4.2V input voltage, 10V - 14V output voltage and 30mA - 300mA load current range, simulated results show that the switching frequency keeps constant at 960kHz to within ±5% across the whole operation range.

This paper presents an error amplifier structure to improve load regulation of low-voltage low-dropout regulators. The proposed error amplifier has ultrawide swing to extend the high-gain region so that the size of power transistor can be reduced. Experimental results show that the required power transistor size is reduced by 25% to achieve similar performance in load regulation. Moreover, extra power consumption and increase of silicon area are not significant.

An integrated boost DC/DC converter that provides two different outputs with a 1.8V input using only one inductor is presented. The converter works in discontinuous conduction mode and employs time division multiplexing in switching the inductor current to the two outputs. Synchronous rectification for high efficiency is implemented. Techniques for current sensing, inductor ringing suppression and controller design are discussed. At an oscillator frequency of 1MHz, the conversion efficiency reaches 90% at 350mW.

An IC controller in a standard 2 /spl mu/m CMOS process implementing the phase-controlled dimmable electronic ballast scheme for compact fluorescent lamps is presented. It features alternate power cycle sensing and closed-loop control for stable change in lamp intensity from full brightness down to 5%.

This paper proposes a novel voltage-control scheme to improve the slow dynamic response of the conventional pulse-width-modulation (PWM) continuous-current-mode (CCM) voltage-programming DC-DC converter. By introducing a high-pass notch filter in the control loop of the conventional converter, the unity gain bandwidth of the loop gain is enhanced and the system Q value is decreased. To demonstrate the improvement in the transient response, voltage-programming PWM CCM DC-DC converters with both the conventional and the proposed control schemes are designed and simulated. Results show that the dynamic response has 10 times improvement.

This paper introduces an alternative structure to implement damping-factor-control frequency compensation for three-stage amplifiers. A theoretical analysis is presented, and experimental results are included. From the experimental results, the new structure provides better phase margin and power supply rejection ratio but higher power consumption and larger chip area are required.