This paper presents Si/SiGe:C and InP/GaAsSb HBTs which feature specific assets to address submillimeter-wave and THz applications. Process and modeling status and challenges are reviewed. The specific topics of thermal and substrate effects, reliability, and HF measurements are also discussed.

A technology roadmap for the electrical performance of high-speed silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) is presented based on combining the results of various 1-D, 2-D, and 3-D technology computer-aided design (TCAD) simulation tools with geometry scalable compact modeling. The latter, including all known parasitic effects, enables the accurate determination of the figures of merit for both devices and selected benchmark circuits. The presented roadmap defines five major technology nodes with the maximum oscillation frequency of a typical high-frequency device structure as the main device design target under the constraints of various other parameters for generating the doping profiles and for defining the lateral scaling factors. An extensive and consistent set of technology and electrical parameters is provided along with the obtained scaling rules. The expected fabrication-related challenges and possible solutions for achieving the predicted performance are being discussed. It is hoped that the presented roadmap will be useful not only for foundries and equipment manufacturers but also for circuit and system designers enabling better predictions of the capability of SiGe-BiCMOS process technology for new millimeter-wave (mm-wave) and terahertz (THz) applications.

This paper presents an emitter follower only track and hold amplifier (THA) in 0.25/spl mu/m SiGe BiCMOS complementary HBT technology. By using a sequence of pnp and npn emitter followers (pnp-npn EF), we enhance the linearity of the THA input buffer for an input signal of 2Vpp. The THA achieves 8bits of accuracy at 10GHz of sampling rate with a 3GHz 2Vpp input signal. This is about three bits more than currently reported 10GS/s THAs in npn-only technology at this wide signal swing.

This paper describes automated methods for generating and editing triangular meshes based on a heuristic approach. These algorithms yield a triangulation that allows the solution of the two dimensional semiconductor device equations very efficiently. Compared to commonly used concepts, our method delivers a smaller number of nodes combined with an excellent representation of the device geometry and an acceptable numeric quality of triangular elements. For this purpose, a priori known anisotropic solution behavior of the device equations at doping fronts, p-n junctions, and material interfaces is consequently exploited in generating the initial grid. Furthermore, appropriate tools for the refinement of the merged grids are presented.