Vehicular cloud (VC) is a promising technology for processing computation-intensive applications (CI-Apps) on smart vehicles. Implementing VCs over the network edge faces two key challenges: (C1) On-board computing resources of a single vehicle are often insufficient to process a CI-App; (C2) The dynamics of available resources, caused by vehicles’ mobility, hinder reliable CI-App processing. This work is among the first to jointly address (C1) and (C2), while considering two common CI-App graph representations, directed acyclic graph (DAG) and undirected graph (UG). To address (C1), we consider partitioning a CI-App with$m$dependent (sub-)tasks into$k\le m$groups, which are dispersed across vehicles. To address (C2), we introduce a generalized reliability metric called conditional mean time to failure (C-MTTF). Subsequently, we increase the C-MTTF of dependent sub-tasks processing via introducing a general framework of redundancy-based processing of dependent sub-tasks over semi-dynamic VCs (RP-VC). We demonstrate thatRP-VCcan be modeled as a non-trivial semi-Markov process (SMP). To analyze this SMP model and its reliability, we develop a novel mathematical framework, called event stochastic algebra ($\langle e\rangle $-algebra). Based on$\langle e\rangle $-algebra, we propose decomposition theorem (DT) to transform the presented SMP to a decomposed SMP (D-SMP). We subsequently calculate the C-MTTF of our methodology. We demonstrate that$\langle e\rangle $-algebra and DT are general mathematical tools that can be used to analyze other cloud-based networks. Simulation results reveal the exactness of our analytical results and the efficiency of our methodology in terms of acceptance and success rates of CI-App processing.

Reuse distance analysis (RDA) is a popular method for calculating locality profiles and modeling cache performance. The present article proposes a framework to apply the RDA algorithm to obtain reuse distance profiles in graphics processing unit (GPU) kernels. To study the implications of hardware-related parameters in RDA, two RDA algorithms were employed, including a high-level cache-independent RDA algorithm, called HLRDA, and a detailed RDA algorithm, called DRDA. DRDA models the effects of reservation fails in cache blocks and miss status holding registers to provide accurate cache-related performance metrics. In this case, the reuse profiles are cache-specific. In a selection of GPU kernels, DRDA obtained the L1 miss-rate breakdowns with an average error of 3.86% and outperformed the state-of-the-art RDA in terms of accuracy. In terms of performance, DRDA is 246,000× slower than the real GPU executions and 11× faster than GPGPU-Sim. HLRDA ignores the cache-related parameters and its obtained reuse profiles are general, which can be used to calculate miss rates in all cache sizes. Moreover, the average error incurred by HLRDA was 16.9%.

This paper presents a 32-bit fault-tolerant (FT) embedded system based on commercial off-the-shelf (COTS) processors. This embedded system uses two 32-bit Pentium/spl reg/ processors with master/checker (M/C) configuration and an external watchdog processor (WDP) for implementing a behavioral-based error detection scheme called committed instructions counting (CIC). The experimental evaluation was performed using both power-supply disturbance (PSD) and software-implemented fault injection (SWIFI) methods. A total of 9000 faults have been injected into the embedded system to measure the coverage of error detection mechanisms, i.e., the checker processor and the CIC scheme. The results show that the M/C configuration is not enough for this system and the CIC scheme could cover the limitation of the M/C configuration.

To enhance the error detection capability in COTS (commercial off-the-shelf)-based design of safety-critical systems, a new hardware-based control flow checking (CFC) technique is presented. This technique, control flow checking by execution tracing (CFCET), employs the internal execution tracing features available in COTS processors and an external watchdog processor (WDP) to monitor the addresses of taken branches in a program. This is done without any modification of application programs, therefore, the program overhead is zero. The external hardware overhead is about 3.5% using an Altera Flex 10K30 FPGA. For different workload programs, the execution time overhead and the error detection coverage of the technique vary between 33.3 and 140.8% and between 79.7 and 84.6% respectively. The errors are detected with about zero latency.

Increasing use of commercial off-the-shelf (COTS) superscalar processors in industrial, embedded, and real-time systems necessitates the development of error detection mechanisms for such systems. This shows an error detection scheme called committed instructions counting (CIC) to increase error detection in such systems. The scheme uses internal performance monitoring features and an external watchdog processor (WDP). The performance monitoring features enable counting the number of committed instructions in a program. The scheme is experimentally evaluated on a 32-bit Pentium/spl reg/ processor using software implemented fault injection (SWIFI). A total of 8181 errors were injected into the Pentium/spl reg/ processor. The results show that the error detection coverage varies between to 90.92% and 98.41%, for different workloads.