EDBT 2026 Demo / reviewers in the wild / expert
Xun Gong 0011
dblp:58/5901-11
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 2019
0000-0003-0417-8028ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
GPUs and heterogeneous computing · 50% Processor architecture and microarchitecture · 50% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing
GPU microarchitecture |
0.4 | 1 | 2019 | HAWS: Accelerating GPU Wavefront Execution through Selective Out-of-order Execution · ACM Trans. Archit. Code Optim. 2019 |
Processor architecture and microarchitecture
latency hiding |
0.4 | 1 | 2019 | HAWS: Accelerating GPU Wavefront Execution through Selective Out-of-order Execution · ACM Trans. Archit. Code Optim. 2019 |
Processor architecture and microarchitecture
out-of-order execution |
0.4 | 1 | 2019 | HAWS: Accelerating GPU Wavefront Execution through Selective Out-of-order Execution · ACM Trans. Archit. Code Optim. 2019 |
GPUs and heterogeneous computing › GPU scheduling
warp scheduling |
0.4 | 1 | 2019 | HAWS: Accelerating GPU Wavefront Execution through Selective Out-of-order Execution · ACM Trans. Archit. Code Optim. 2019 |
Compilers and program optimization › compiler optimization
compiler-directed optimization |
0.1 | 1 | 2019 | HAWS: Accelerating GPU Wavefront Execution through Selective Out-of-order Execution · ACM Trans. Archit. Code Optim. 2019 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2019 | HAWS: Accelerating GPU Wavefront Execution through Selective Out-of-order ExecutionabstractGraphics Processing Units (GPUs) have become an attractive platform for accelerating challenging applications on a range of platforms, from High Performance Computing (HPC) to full-featured smartphones. They can overcome computational barriers in a wide range of data-parallel kernels. GPUs hide pipeline stalls and memory latency by utilizing efficient thread preemption. But given the demands on the memory hierarchy due to the growth in the number of computing cores on-chip, it has become increasingly difficult to hide all of these stalls. In this article, we propose a novel Hint-Assisted Wavefront Scheduler (HAWS) to bypass long-latency stalls. HAWS starts by enhancing a compiler infrastructure to identify potential opportunities that can bypass memory stalls. HAWS includes a wavefront scheduler that can continue to execute instructions in the shadow of a memory stall, executing instructions speculatively, guided by compiler-generated hints. HAWS increases utilization of GPU resources by aggressively fetching/executing speculatively. Based on our simulation results on the AMD Southern Islands GPU architecture, at an estimated cost of 0.4% total chip area, HAWS can improve application performance by 14.6% on average for memory intensive applications. Xun Gong 0011, Leiming Yu, David R. Kaeli |
ACM Trans. Archit. Code Optim. | 1 |
| 2017 | Multi2Sim Kepler: A detailed architectural GPU simulatorabstractPresilicon simulation is one of the key toolsets for computer architects to evaluate and optimize their future designs. As Graphics Processing Units (GPUs) have become the platform of choice in many computing communities due to their impressive processing capabilities, computer architecture researchers need a simulation framework that allows them to quantitatively consider design tradeoffs. In this paper, we present the Multi2Sim Kepler simulator framework, a new detailed GPU microarchitecture performance simulator that supports NVIDIA's Kepler shader assembly (SASS) code execution. The toolset provides a disassembler, a functional simulator and a detailed cycle-based simulator. We provide insight into the architecture of the NVIDIA Kepler GPU, describing the details of the streaming multiprocessor, front-end and instruction pipelines. We compare the performance of this new simulator against an NVIDIA K20X, a high-end Kepler device. We also evaluate the performance of NVIDIA's CUDA benchmark suite on our GPU performance simulator. Xun Gong 0011, Rafael Ubal, David R. Kaeli |
ISPASS | 1 |