The complexity of the state-of-the-art devices makes reliability assessments approaches extremely complex and, sometimes, out of the timing constraints and computational capabilities. Fault Injections (FIs) are one of the most used approaches for evaluating the dependability of safety-critical systems. With billion-transistor hardware devices running trillion-parameter deep neural networks, injecting the entire fault universe is unfeasible. A widespread solution consists in performing statistical fault injections (SFIs), injecting a subset of faults to estimate a characteristic with an error margin and a confidence level. This research work presents an iterative SFI approach to estimate failure rates in convolutional neural networks (CNNs), i.e., the percentage of wrong predictions caused by random hardware faults affecting synaptic weights. SFIs at different granularities have been performed with margin of errors equal to 1%, 0.1%, and 0.01%. Results for two CNNs (ResNet20 and MobileNetV2) are presented and experimentally and statistically demonstrate the effectiveness of the proposed approach. For instance, to estimate the network-wise failure rate with an error margin of 0.01%, the proposed approach reduces the total injected faults by about 66% and 90% compared to conservative methods, and by 1.94% and 1.65% compared to iterative SFI methods in the literature, for ResNet20 and MobileNetV2, respectively.

Assessing the reliability of modern devices running CNN algorithms is a very difficult task. Actually, the complexity of the state-of-the-art devices makes exhaustive Fault Injection (FI) campaigns impractical and typically out of the computational capabilities. A possible solution consists of resorting to statistical FI campaigns that allow a reduction in the number of needed experiments by injecting only a carefully selected small part of it. Under specific hypothesis, statistical FIs guarantee an accurate picture of the problem, albeit selecting a reduced sample size. The main problems today are related to the choice of the sample size, the location of the faults, and the correct understanding of the statistical assumptions. The intent of this paper is twofold: first, we describe how to correctly specify statistical FIs for Convolutional Neural Networks; second, we propose a data analysis on the CNN parameters that drastically reduces the number of FIs needed to achieve statistically significant results without compromising the validity of the proposed method. The methodology is experimentally validated on two CNNs, ResNet-20 and MobileNetV2, and the results show that a statistical FI campaign on about 1.21% and 0.55% of the possible faults, provides very precise information of the CNN reliability. The statistical results have been confirmed by the exhaustive FI campaigns on the same cases of study.

The widespread use of artificial intelligence (AI)-based systems has raised several concerns about their deployment in safety-critical systems. Industry standards, such as ISO26262 for automotive, require detecting hardware faults during the mission of the device. Similarly, new standards are being released concerning the functional safety of AI systems (e.g., ISO/IEC CD TR 5469). Hardware solutions have been proposed for the infield testing of the hardware executing AI applications; however, when used in applications such as Convolutional Neural Networks (CNNs) in image processing tasks, their usage may increase the hardware cost and affect the application performances. In this paper, for the very first time, a methodology to develop high-quality test images, to be interleaved with the normal inference process of the CNN application is proposed. An Image Test Library (ITL) is developed targeting the on-line test of GPU functional units. The proposed approach does not require changing the actual CNN (thus incurring in costly memory loading operations) since it is able to exploit the actual CNN structure. Experimental results show that a 6-image ITL is able to achieve about 95% of stuck-at test coverage on the floating-point multipliers in a GPU. The obtained ITL requires a very low test application time, as well as a very low memory space for storing the test images and the golden test responses.

This paper encompasses three contributions by industry professionals and university researchers. The contributions describe different trends in automotive products, including both manufacturing test and run-time reliability strategies. The subjects considered in this session deal with critical factors, from optimizing the final test before shipment to market to in-field reliability during operative life.

The current demands for autonomous driving generated momentum for an increase in research in the different technologies required for these applications. Nonetheless, the limited access to representative designs and industrial methodologies poses a challenge to the research community. Considering this scenario, there is a high demand for an open-source solution that could support development of research targeting automotive applications. This paper presents the current status of AutoSoC, an automotive SoC benchmark suite that includes hardware and software elements and is entirely open-source. The objective is to provide researchers with an industrial-grade automotive SoC that includes all essential components, is fully customizable, and enables analysis of functional safety solutions and automotive SoC configurations. This paper describes the available configurations of the benchmark including an initial assessment for ASIL B to D configurations.

Since the early 1990s, federated avionics architecture - where one computing resource executes only one application, is being replaced by Integrated Modular Avionics (IMA) architectures. IMA architectures employ a partitioned environment that hosts multiple avionics functions of different safety criticalities on a common computing platform. This provides for size, weight, and power savings via denser functional integration. Several cores integrated onto one device allows more functions to be integrated together on one processor and in one piece of equipment. The use of multicore processors in safety-critical avionics applications will provide growth for further integration for the future generations of these systems. Hence aerospace equipment suppliers are interested in using Multi-Core Processors (MCPs) in their systems. With the rapid increase in demand for computational performance and cost optimum, Single-Core Processors (SCPs) are likely to become obsolete. However, with the shift to multi-core processors, compliance to safety requirements is becoming critical. The development and use of increasingly complex electronic hardware by the aviation industry for more of the safety-critical aircraft functions is creating new safety and certification concerns.

Cross-layer reliability is becoming the preferred solution when reliability is a concern in the design of a microprocessor-based system. Nevertheless, deciding how to distribute the error management across the different layers of the system is a very complex task that requires the support of dedicated frameworks for cross-layer reliability analysis. This paper proposes SyRA, a system-level cross-layer early reliability analysis framework for radiation induced soft errors in memory arrays of microprocessor-based systems. The framework exploits a multi-level hybrid Bayesian model to describe the target system and takes advantage of Bayesian inference to estimate different reliability metrics. SyRA implements several mechanisms and features to deal with the complexity of realistic models and implements a complete tool-chain that scales efficiently with the complexity of the system. The simulation time is significantly lower than micro-architecture level or RTL fault-injection experiments with an accuracy high enough to take effective design decisions. To demonstrate the capability of SyRA, we analyzed the reliability of a set of microprocessor-based systems characterized by different microprocessor architectures (i.e., Intel x86, ARM Cortex-A15, ARM Cortex-A9) running both the Linux operating system or bare metal in the presence of single bit upsets caused by radiation induced soft errors. Each system under analysis executes different software workloads both from benchmark suites and from real applications.

Modern cars consist of a number of complex embedded and networked systems with steadily increasing requirements in terms of processing and communication resources. Novel automotive applications, such as automated driving, rise new needs and novel design challenges that cover a broad range of hardware/software engineering aspects. In this context, this paper provides an overview of the current technological challenges in on-board and networked automotive systems. This paper encompasses both the state-of-the-art design strategies and the upcoming hardware/software solutions for the next generation of automotive systems, with a special focus on embedded and networked technologies. In particular, this paper surveys current solutions and future trends on models and languages for automotive software development, on-board computational platforms, in-car network architectures and communication protocols, and novel design strategies for cybersecurity and functional safety.

The papers in this special section focus on embedded and networked systems for intelligent vehicles and robots. Embedded and networked systems for intelligent vehicles and robots are expected to have a significant economic, societal, and technological impact on industrial and automotive applications. Among the aspects that will benefit from these technologies the first one is safety, thanks to the reduction of accidents caused by human errors. Another positive effect is expected on sustainability, thanks to the increase in transport systems efficiency. Comfort and inclusiveness will be also improved, ensuring users’ freedom for other activities and “mobility for all.” Logistics and factory automation are among the main areas that will take advantages from intelligent vehicles and robots, that are expected to play a key role in Industry 4.0 scenarios, the so-called fourth industrial revolution, where intelligent vehicles and industrial robots will move and operate autonomously and cooperatively. Such a revolution has many key enabling technologies, such as, networked sensors, actuators, and embedded computing and control platforms, that will be distributed on-board the vehicle/robot. The contribution of artificial intelligence and deep learning computing platforms is also emerging to achieve full intelligent autonomous mobility of vehicles and robots.

Advanced multifunctional computing systems realized in forthcoming technologies hold the promise of a significant increase of the computational capability that will offer end-users ever improving services and functionalities (e.g., next generation mobile devices, cloud services, etc.). However, the same path that is leading technologies toward these remarkable achievements is also making electronic devices increasingly unreliable, posing a threat to our society that is depending on the ICT in every aspect of human activities. Reliability of electronic systems is therefore a key challenge for the whole ICT technology and must be guaranteed without penalizing or slowing down the characteristics of the final products. CLERECO EU FP7 (GA No. 611404) research project addresses early accurate reliability evaluation and efficient exploitation of reliability at different design phases, since these aspects are two of the most important and challenging tasks toward this goal.

Evaluation of computing systems reliability must be accurate enough to provide hints for the required fault protection mechanisms that will guarantee correctness of operation at acceptance costs. To be useful, reliability evaluation must be performed early enough in the design cycle when, however, the available details of the system are largely unknown. This inherent contradiction in terms: early vs. accurate, requires a cross-layer approach for reliability evaluation. Different layers of abstraction contribute differently in the overall system reliability; if this contribution can be assessed independently, the reliability of the system can be evaluated at the early stages of the design. We review the state-of-the-art in the area and discuss corresponding challenges .

Summary form only given. The major bottleneck for technology scaling is the growing rate of hardware failures. Process variations are becoming extreme and sensitivity to radiation is becoming severe. In addition, intrinsic failures such as device parameter degradation are accelerating the wear-out. All of these are leading to higher random in-filed failures and shorter device lifetime. The 2011 ITRS (International Technology Roadmap for Semiconductors) projects very high bit failure rates of the order of 10-2for SRAM and of 10-3for latches for 16nm high performance technology. Hence, solving reliability challenges for future technologies requires new efficient and cost effective approaches not only to detect and recover from in-filed failures, but also to extend the device lifetime for targeted applications.

The panel gives an overview of requirements, problems and solutions related to the application of ISO 26262 (the international norm ruling functional safety for automotive) and IEC 61508 2nd edition (the international norm widely used in industrial domain) to the design and test of integrated circuits.

Performance demand of Critical Real-Time Embedded (CRTE) systems implementing safety-related system features grows at an exponential rate. Only modern semiconductor technologies can satisfy CRTE systems performance needs efficiently. However, those technologies lead to high failure rates, thus lowering survivability of chips to unacceptable levels for CRTE systems. This paper presents SESACS architecture (Surviving Errors in SAfety-Critical Systems), a paradigm shift in the design of CRTE systems. SESACS is a new system design methodology consisting of three main components: (i) a multicore hardware/firmware platform capable of detecting and diagnosing hardware faults of any type with minimal impact on the worst-case execution time (WCET), recovering quickly from errors, and properly reconfiguring the system so that the resulting system exhibits a predictable and analyzable degradation in WCET; (ii) a set of analysis methods and tools to prove the timing correctness of the reconfigured system; and (iii) a white-box methodology and tools to prove the functional safety of the system and compliance with industry standards. This new design paradigm will deliver huge benefits to the embedded systems industry for several decades by enabling the use of more cost-effective multicore hardware platforms built on top of modern semiconductor technologies, thereby enabling higher performance, and reducing weight and power dissipation. This new paradigm will further extend the life of embedded systems, therefore, reducing warranty and early replacement costs.

Dependability, availability, reliability and security (in a single word, robustness) are primary-importance elements for today's Systems-on-Chip (SoCs), in different areas. To achieve robustness, functional blocks are combined with fault-detection and fault-tolerance circuits to detect or correct faults due to environmental impact, aging, soft-errors and so forth. Furthermore, systematic faults (i.e. fault whose failure is manifested in a deterministic way) shall be avoided. Fault-detection and fault-tolerance circuits' verification is the key to achieve that goal. This paper summarizes the state-of-the-art for verification-by-simulation flow, to subsequently extend the verification strategy for fault-detection and fault-tolerance circuits.

In the near future the automotive systems will include microcontrollers hosting homogeneous or heterogeneous multi-core architectures, in which two or more CPU cores are combined to satisfy the high performance requirements. For those devices, time dependability issues represent a key challenge. In addition to that, they shall satisfy standards like ISO 26262 for functional safety and AUTOSAR for software architectures. This paper focuses on the study of problems and solutions related to functional-safe timing-dependable real-time architectures; in particular we identify critical failures related to timing issues and we propose a functional-safety aware methodology combining HW and SW measures to handle such kind of failures.

Microprocessors performances have increased by more than five orders of magnitude in the last three decades. As technology scales down, these components become inherently unreliable posing major design and test challenges. This paper proposes an instruction-checking architecture to detect erroneous instruction executions caused by both permanent and transient errors in the internal logic of a microprocessor. Monitoring the correct activation sequence of a set of predefined microprocessor control/status signals allow distinguishing between correctly and not correctly executed instructions.

This paper proposes an innovative methodology to perform and validate a failure mode and effects analysis (FMEA) at system-on-chip (SoC) level. This is done in compliance with the IEC 61508, an international norm for the functional safety of electronic safety-related systems, of which an overview is given in the paper. The methodology is based on a theory to decompose a digital circuit in "sensible zones" and a tool that automatically extracts these sensible zones from the RTL description. It includes as well a spreadsheet to compute the metrics required by the IEC norm such diagnostic coverage and safe failure fraction. The FMEA results are validated by using another tool suite including a fault injection environment. The paper explains how to take benefits of the information provided by such approach and as example it is described how the methodology has been applied to design memory sub-systems to be used in fault robust microcontrollers for automotive applications. This methodology has been approved by TUV-SUD as the flow to assess and validate the safe failure fraction of a given SoC in adherence to IEC 61508

This paper proposes a method to perform failure mode and effects analysis (FMEA) on system-on- chips (SoC). An automatic tool extracts information from the SoC description and uses them to estimate the intrinsic criticality of invariant and elementary "sensitive zones " and to compute metrics such failure rates, safe failures fraction and diagnostic coverage. A validation flow based on fault injection and fault simulation is included to cross check the FMEA.

The design space that a system architect should manage when designing a microcontroller for a safety related system is rather large due to the variety of faults that can affect the given equipment under control (EUC), the different failures that these faults can generate and the wide set of techniques that can be used to detect, confine or stop the resulting hazards, each one with its efficiency and cost. In this paper it is proposed a systematic platform-based approach, in which a library of blocks (HW and SW) is used together with a set of tools and methodologies to find the optimum solution in this design space, following the IEC61508 guidelines

Based on the definition of a mission vulnerability factor, this paper proposes the use of on-line memory scrubbing technique joined with memory partitioning, describing how such approach can help to reduce overhead and performance penalties of ECC-based protection systems.

This paper presents a fault injection tool developed to evaluate different DSP-based architectures for space applications. The evaluation addresses mainly the ability of the different architectures to detect Single-Event-Upset (SEU) faults induced by space radiation.

This paper presents the test strategy adopted at different hierarchical abstraction levels (from board to die level) during the development of a multichannel data acquisition and signal processing MCM, designed for the new generation experiments of high-energy physics on the Large Hadron Collider accelerator at CERN.