Temporal dependencies between multiple sensor data sources link two types of events if the occurrence of one is repeatedly followed by the appearance of the other in a certain time interval. TEDDY algorithm aims at discovering such dependencies, identifying the statically significant time intervals with a chi2 test. We present how these dependencies can be used within the GrizzLY project to tackle an environmental and technical issue: the deicing of the roads. This project aims to wisely organize the deicing operations of an urban area, based on several sensor network measures of local atmospheric phenomena. A spatial and temporal dependency-based model is built from these data to predict freezing alerts.

SUMMARY Recent advances in information theory and networking, e.g. aggregation, network coding or rateless codes, have significantly modified data dissemination in wireless networks. These new paradigms create new threats for security such as pollution attacks and denial of services (DoS). These attacks exploit the difficulty to authenticate data in such contexts. The particular case of xor network coding is considered herein. We investigate different strategies based on message authentication codes algorithms (MACs) to thwart these attacks. Yet, classical MAC designs are not compatible with the linear combination of network coding. Fortunately, MACs based on universal hash functions (UHFs) match nicely the needs of network coding: some of these functions are linear h(x1⊕x2) = h(x1)⊕h(x2). To demonstrate their efficiency, we consider the case of wireless sensor networks (WSNs). Although these functions can drastically reduce the energy consumption of authentication (up to 68% gain over the classical designs is observed), they increase the threat of DoS. Indeed, an adversary can disrupt all communications by polluting few messages. To overcome this problem, a group testing algorithm is introduced for authentication resulting in a complexity linear in the number of attacks. The energy consumption is analyzed for cross‐point and butterfly network topologies with respect to the possible attack scenarios. The results highlight the trade‐offs between energy efficiency, authentication and the effective throughput for the different MAC modes. Copyright © 2011 John Wiley & Sons, Ltd.

This paper presents a system design study for wearable sensor devices intended for healthcare and lifestyle applications based on ECG, EEG and activity monitoring. In order to meet the low-power requirement of these applications, a dual-core signal processing system is proposed which combines an ultra-low-power bio-medical Application Specific Instruction-set Processor (BioASIP) and a low-power general-purpose micro-controller (MSP430). To validate the merits of the proposed architecture, system-level power analysis and trade-offs are conducted using real hardware measurements of an ECG R-peak detection application. The results show that the proposed dual-core architecture consumes around 65.38µW, about 25.8x smaller than an MSP430-only approach. Out of 65.38µW, the BioASIP consumes only 11µW and the rest is used in the analog front-end, A/D conversion, and control tasks.

This paper presents a description of SensLAB(Very Large Scale Open Wireless Sensor Network Testbed) that has been developed and deployed in order to allow the evaluation through experimentations of scalable wireless sensor network protocols and applications. SensLAB’s main and most important goal is to offer an accurate open access multi-users scientific tool to support the design, the development tuning, and the experimentation of real large-scale sensor network applications. The SensLAB testbed is composed of 1024 nodes over 4 sites. Each site hosts 256 sensor nodes with specific characteristics in order to offer a wide spectrum of possibilities and heterogeneity. Within a given site, each one of the 256 nodes is able both to communicate via its radio interface to its neighbors and to be configured as a sink node to exchange data with any other ” sink node ”. The hardware and software architectures that allow to reserve, configure, deploy firmwares and gather experimental data and monitoring information are described. We also present demonstration examples to illustrate the use of the SensLAB testbed and encourage researchers to test and benchmark their applications/protocols on a large scale WSN testbed.

The recent advances in information theory and networking have significantly modified the way to disseminate data in wireless sensor networks (WSNs): aggregation, network coding or rateless codes. These new paradigms of dissemination create new threats for security such as pollution attacks. These attacks exploit the difficulty to protect data integrity in those contexts. In this paper, we consider the particular case of xor network coding. We compare the different strategies based on message authentication codes algorithms (MACs) to thwart these attacks. We emphasize the advantages of universal hash functions (UHFs) in terms of flexibility and efficiency. These schemes reduce the energy consumption by 42% and 68% (according to the used protocol) for the relaying nodes over those based on classical cryptographic primitives without any loss in security. The key feature of the UHFs considered here is their homomorphic property (h(x1⊕ x2)=h(x1) ⊕ h(x2)). These homomorphic MACs offer more possibilities for the relying nodes than the classical cryptographic ones: the detection time of a pollution attack can be adjusted to preserve the nodes energy. Moreover, they can be computed with the low resources of a sensor.

Instead of a single circuit dedicated to a particular physical (PHY) layer standard, a Software Defined Radio (SDR) platform embeds several hardware accelerators which enable it to support different modulation schemes. In this study we propose an architecture for a SDR PHY layer based on the Virtual Machine (VM) concept. Once a program is compiled in a portable byte-code, the VM can then execute it to manage the desired PHY layer. We demonstrate the feasibility of the proposed architecture through a case study and a proof-of-concept implementation.

We present Worldsens,a prototyping and development work for wireless sensor protocols and applications.Our relies on two simulators,WSim and WSNet, and proposes a full simulation and performance estimation embedded platforms with instruction and radio byte curacy.During this demo,we propose to demonstrate the interest of the two simulators in stand-alone and in cooperative use.

In this paper we present Worldsens, an integrated environment for development and rapid prototyping of wireless sensor network applications. Our environment relies on software simulation to help the designer during the whole development process. The refinement is done starting from the high level design choices down to the target code implementation, debug and performance analysis. In the early stages of the design, high level parameters, like for example the node sleep and activity periods, can be tuned using WS-Net, an event driven wireless network simulator. WSNet uses models for applications, protocols and radio medium communication with a parameterized accuracy. The second step of the sensor network application design takes place after the hardware implementation choices. This second step relies on the WSim cycle accurate hardware platform simulator. WSim is used to debug the application using the real target binary code. Precise performance evaluation, including real-time analysis at the interrupt level, are made possible at this low simulation level. WSim can be connected to WSNet, in place of the application and protocol models used during the high level simulation to achieve a full distributed application simulation. WSNet and WSNet+WSim allow a continuous refinement from high level estimations down to low level real-time validation. We illustrate the complete application design process using a real life demonstrator that implements a hello protocol for dynamic neighborhood discovery in a wireless sensor network environment.

This paper presents a performance and energy consumption simulator for deeply embedded hardware platforms such as sensor network nodes. These tools are based on cycle accurate simulation of complete hardware platforms executing the real application code. This allows designers to get fast performance and consumption estimations without deploying software on target hardware, while being independent of any compilation tools or software components such as network protocols or operating systems.

In the process of mapping compute-intensive algorithms onto arrays of processing elements (PEs) an efficient usage of channels between PEs and registers within PEs is crucial for achieving a significant algorithm acceleration. In this paper this problem is solved for algorithms represented as systems of uniform recurrence equations. We address an optimization problem in order to realize the algorithmic data dependencies within the processor array (PA) with minimum cost for channels and registers. There, we use a new mapping approach which allows a direct mapping of the algorithm onto the PA by a partitioning method. In contrast to existing approaches, the authors consider the issue of avoiding redundant usage of channels and registers, which can appear if one instance of a variable has to be transferred from a source PE to several sink PEs. Further, a solution of the optimization problem determines the schedule for the transfer of the variable instances in the channels and their storage in registers as well as the inner schedule for the operations in the PEs. We illustrate our method on the edge detection algorithm

Translation of assembly code to high-level language code is of importance in the maintenance of legacy code, as well as in the areas of program understanding, porting, and recovery of code. We present techniques used in the asm2c translator, a SPARC assembly to C translator. The techniques involve data and control flow analyses. The data flow analysis eliminates machine dependencies from the assembly code and recovers high-level language expressions. The control flow analysis recovers control structure statements. Simple data type recovery is also done. The presented techniques are extensions and improvements on previously developed CISC techniques. The choice of intermediate representation allows for both RISC and CISC assembly code to be supported by the analyses. We tested asm2c against SPEC95 SPARC assembly programs generated by a C compiler. Results using both unoptimized and optimized assembly code are presented.

Program slicing is a technique for determining the set of statements of a program that potentially affect the value of a variable at some point in the program. Intra and interprocedural slicing of high level languages has greatly been studied in the literature; both static and dynamic techniques have been used to aid in the debugging, maintenance, parallelization, program integration, and dataflow testing of programs. We explain how to apply conventional intraprocedural static analysis to binary executables for the purposes of static analysis of machine code and assembly code, such as debugging code and determining the instructions that affect an indexed jump or an indirect call on a register. This analysis is useful in the decoding of machine instructions phase of reverse engineering tools of binary executables, such as binary translators, disassemblers, binary profilers and binary debuggers