Abstract A software behavioural simulator for a new massively parallel single‐instruction/multiple data (SIMD) architecture has been developed that can accurately simulate the entire 16, 384 bit‐serial processor array. The key to this high performance modelling is the exploitation of an inherent mapping that exists between massively parallel SIMD architectures and the vector architectures used in many high performance scientific super‐computers. The new SIMD architecture, called BLITZEN, is based on the Massively Parallel Processor (MPP) built for NASA by Goodyear in the late 1970s. By simulating the full‐scale machine with very high performance, the simulator allows development of algorithms and high‐level software to proceed before realization of the hardware. This paper describes the SIMD ‐ vector architecture mapping, the highly vectorized simulator in which it is used, and how the result was a simulator that achieved a level of performance three orders of magnitude faster than the conventional uniprocessor approach.

This paper is about the software engineering facets of the making of a large programming systems product for symbolic VLSI CAD called VIVID. Issues such as how teams were organized, how conceptual integrity was maintained, and portability are discussed. Specific tools are also described that were built to aid in the development of VIVID. Methods are explored that aid in managing large systems with many directories and huge numbers of files. Finally, techniques for debugging such a large system are discussed. This paper's goal is to share these tools, techniques and methods to improve the software engineering practices used by all developers of CAD as well as other large software systems.

This paper describes the VIVID (Vertically Integrated VLSI Design) System developed at the Microelectronics Center of North Carolina. The system is based on a symbolic, virtual-grid design methodology that greatly reduces the design time for custom VLSI circuits. This methodology has made it possible to provide, in a single integrated system, several unique features: technology independent tools for a wide range of MOS processes (CMOS, nMOS, SOI); scale independent circuit designs; open architecture that simplifies both integration with existing tools and creation of new tools; fast layout debugging using symbolic level circuit simulation; and fully automated mask generation and automated chip assembly.

An effective heuristic has been developed that provides an auto-interactive process to translate schematic net-lists to symbolic layouts. A net-list description of the logic-level of a circuit is the starting point for the process. This net-list initializes the symbolic layout system by providing device and pin names — position information is provided interactively by the designer. The designer places these active elements by name and then makes the connections between them. As each connection is made a check is performed to verify that electrical connectivity of the layout exactly matches that of the net-list and the original schematic.

This paper compares three data structures that support area operations on 2-space: linked lists, quad trees, and multidimensional binary trees (k-d trees). Region searching is the most important operation these data structures must support in many applications. Insertion and deletion must also be reasonably fast. The three data structures are described and implementation considerations are discussed. Extensive experimentation was done using an experimental program that executed algorithms for all three data structures on the same problem. Results of this experimentation is presented to show the superior performance of k-d trees. The conclusion of this paper is that in applications where region search (or point search) on large problems is crucial (as in computer-aided design), k-d trees provide superior performance. Quad trees have become quite popular recently to solve the same problem--this may be due to unfamiliarity with k-d trees or a feeling that they are hard to implement. Actual working code for k-d trees (and quad trees) is included in this paper in an attempt to address both these problems.