We will present a partial scan design method based on n-fold line-up structures and a partial scan design method based on the state justification of pure FFs of load/hold type in order to achieve high fault efficiency for practical LSIs. We will also present a dynamic test sequence compaction method for acyclic structures. Experimental results for practical LSIs show that our presented methods can achieve high fault efficiency and reduce the number of test patterns by half.

Proposes a new algorithm of estimation and compensation of the error effect for rounding in the case of implementation of division and square root using the Newton-Raphson method. The authors analyze the error of the hardware system to confirm the condition of the implementation with respect to this algorithm. Next, they describe in detail how to compensate the error by using this algorithm. Finally, they show that the hardware components for this algorithm, the direct rounding mechanism in the recode circuit and the sticky digit generating circuit, can be realized simply by improving the redundant binary representation multiplier. The number of increasing cycles for this new algorithm is only one, and the rounding result using this algorithm satisfies IEEE Standard 754 rounding perfectly.>

A high speed multiplier and divider for MOS LSI based on a new algorithm is presented. When we implement the multiplier and the divider in LSI, the features such as high speed operation, small number of transistors and easy layout are the most important factors. A computational algorithm using a redundant binary representation has several excellent features such as high speed addition operations. We improved the algorithm and the method of implementation, and designed an advanced multiplier and divider with the above mentioned features. We expect mat our multiplier and divider are excellent compared with multipliers using the Booth algorithm and the Wallace tree, and with divider using the SRT method, respectively.