Modern processors improve instruction level parallelism by speculation. The outcome of data and control decisions is predicted, and the operations are speculatively executed and only committed if the original predictions were correct. There are a number of other ways that processor resources could be used, such as threading or eager execution. As the use of speculation increases, we believe more processors will need some form of speculation control to balance the benefits of speculation against other possible activities. Confidence estimation is one technique that can be exploited by architects for speculation control. In this paper, we introduce performance metrics to compare confidence estimation mechanisms, and argue that these metrics are appropriate for speculation control. We compare a number of confidence estimation mechanisms, focusing on mechanisms that have a small implementation cost and gain benefit by exploiting characteristics of branch predictors, such as clustering of mispredicted branches. We compare the performance of the different confidence estimation methods using detailed pipeline simulations. Using these simulations, we show how to improve some confidence estimators, providing better insight for future investigations comparing and applying confidence estimators.

As processor performance continues to improve, more emphasis must be placed on the performance of the memory system. In this paper, a detailed characterization of data cache behavior for individual load instructions is given. We show that by selectively applying cache line allocation according the characteristics of individual load instructions, overall performance can be improved for both the data cache and the memory system. This approach can improve some aspects of memory performance by as much as 60 percent on existing executables.

Presents a trace-driven simulation-based study of a wide range of cache configurations and processor counts. This study was undertaken in an attempt to help answer the question of how best to allocate large numbers of transistors, a question that is rapidly increasing in importance as transistor densities continue to climb. At what point does continuing to increase the size of the on-chip first level cache cease to provide sufficient increases in hit rate and become prohibitively difficult to access in a single cycle? In order to compare different configurations, the concept of an Equivalent Cache Transistor is presented. Results indicate that the access time of the first-level data cache is more important than the size. In addition, it appears that once approximately 15 million transistors become available, a two processor configuration is preferable to a single processor with correspondingly larger caches.>

In this paper a technique for generating consistent, reproducible traces with about an order of magnitude better compression than standard general-purpose compression programs is described. With this approach, the trace is read once, an intermediate form is generated and then read as the input to the second pass over the address stream. No program source code is required, and this technique will work on address streams that include OS calls. As a result of the way the address trace is encoded and processed, representing each reference requires only a fraction of a bit, between 0.00114 to 0.878 bits per reference. For example, the roughly 1.6 billion references generated by the xlisp benchmark from the SPEC92 suite can be stored using only about 48.6 million bytes. Depending on the benchmarks, more or less bits per references may be needed.

This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC architecture uses multiple asynchronous processing elements to separate a program into streams that can be executed in parallel, and integrates a conflict-free message passing system into the lowest level of the processor design to facilitate low latency intra-MISC communication. This approach allows for increased machine parallelism with minimal code expansion, and provides an alternative approach to single instruction stream multi-issue machines such as SuperScalar and VLIW. # # 1. Introduction The goal of most high-performance computers is to maximize the amount of work that can be done per unit time. This quantity (work) can be expressed by the following equation [HePa90]: work = clock rate× instruction count 1 ############### × Clocks per Instruction 1 ################### A number of different approa...

Deeply pipelined processors have relatively low issue rates due to dependencies between instructions. In this paper we examine the possibility of interleaving a second stream of instructions into the pipeline, which would issue instructions during the cycles the first stream was unable to. Such an interleaving has the potential to significantly increase the throughput of a processor without seriously imparing the execution of either process. We propose a dynamic interleaving of at most 2 instructions streams, which share the the pipelined functional units of a machine. To support the interleaving of 2 instruction streams a number of interleaving policies are described and discused. Finally, the amount of improvement in processor throughput is evaluated by simulating the interleaving policies for several machine variants. 1. Introduction An important metric for evaluating processor performance, especially in a multiprocessing context, is the throughput rate of a processor (defined as h...

Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this instruction cache will cause an external memory reference which must compete with data references for access to the external memory, thus affecting the overall performance of the processor. One common way to reduce the number of off-chip instruction requests is to increase the size of the on-chip cache. An alternative approach is presented in this paper, in which a combination of an instruction cache, instruction queue and instruction queue buffer is used to achieve the same effect with a much smaller instruction cache size. Such an approach is significant for emerging technologies where high circuit densities are initially difficult to achieve yet a high level of performance is desired, or for more mature technologies where chip area can be used to provide more functionality. The viability of this approach is demonstrated by its implementation in an existing single-chip processor.

The interaction is investigated of pipelining and multiple-functional units in single-processor machines, to gain an understanding of how each of these techniques contribute to performance improvement. A CRAY-like processor model is studied. The issue rate (instructions per clock cycle) is used as the performance measure. The base, nonpipelined, machine is then systematically augmented with more and more hardware features and the performance impact of each feature is evaluated. It is found that in nonvector machines, pipelining multiple-function units does not provide significant performance improvements. Dataflow limits are then derived for benchmark programs to determine the performance potential of each benchmark. In addition, other limits are computed which apply more realistic constraints on a computation. Based on these more realistic limits, it is determined to be worthwhile to investigate the performance improvements that can be achieved from issuing multiple instructions during each clock cycle. Several hardware approaches are evaluated for issuing multiple instructions each clock cycle.>

Five solutions to the precise interrupt problem in pipelined processors are described and evaluated. An interrupt is precise if the saved process state corresponds to a sequential model of program execution in which one instruction completes before the next begins. In a pipelined processor, precise interrupts are difficult to implement because an instruction may be initiated before its predecessors have completed. The first solution forces instructions to complete and modify the process state in architectural order. The other four solutions allow instructions to complete in any order, but additional hardware is used, so that a precise state can be restored when an interrupt occurs. All the methods are discussed in the context of a parallel pipeline structure. Simulation results for the Cray-1S scalar architecture are used to show that the first solution results in a performance degradation of at least 16%. The remaining four solutions offer better performance, and three of them result in as little as a 3% performance loss. Several extensions, including vector architectures, virtual memory, and linear pipeline structures, are briefly discussed.>

In this paper, the WISQ architecture is described. This architecture is designed to achieve high performance by exploiting new compiler technology and using a highly segmented pipeline. By having a highly segmented pipeline, a very-high-speed clock can be used. Since a highly segmented pipeline will require relatively long pipelines, a way must be provided to minimize the effects of pipeline bubbles that are formed due to data and control dependencies. It is also important to provide a way of supporting precise interrupts. These goals are met, in part, by providing a reorder buffer to help restore the machine to a precise state. The architecture then makes the pipelining visible to the programmer/compiler by making the reorder buffer accessible and by explicitly providing that issued instructions cannot be affected by immediately preceding ones. Compiler techniques have been identified that can take advantage of the reorder buffer and permit a sustained execution rate approaching or exceeding one per clock. These techniques include using trace scheduling and providing a relatively easy way to “undo” instructions if the predicted branch path is not taken. We have also studied ways to further reduce the effects of branches by not having them executed in the execution unit. In particular, branches are detected and resolved in the instruction fetch unit. Using this approach, the execution unit is sent a stream of instructions (without branches) that are guaranteed to execute.

In this paper, we present a Lisp machine architecture that supports efficient list manipulation. This Lisp architecture is organized as two processing units: a List Processor (LP), that performs all list related operations and manages the list memory, and an Evaluation Processor (EP), that maintains the addressing and control environment. The LP contains a translation table (LPT) that maps a small set of list identifiers into the physical memory addresses of objects. Essentially, the LP and LPT virtualize a list. The EP then operates on these virtualized lists. Such an organization permits the overlap of EP function evaluation with LP memory accesses and management, thus reducing the performance penalties typically associated with Lisp list manipulation activities. We used trace-driven simulations to evaluate this architecture. From our evaluation a relatively small LPT is seen to be sufficient, and to yield “hit rates” on data accesses higher than those of a data cache of comparable size.

article Free Access Share on PIPE: a VLSI decoupled architecture Authors: J. R. Goodman The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile , Jian-tu Hsieh The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile , Koujuch Liou The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile , Andrew R. Pleszkun The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile , P. B. Schechter The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile , Honesty C. Young The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile Authors Info & Claims ACM SIGARCH Computer Architecture NewsVolume 13Issue 3June 1985 pp 20–27https://doi.org/10.1145/327070.327117Published:01 June 1985Publication History 101citation592DownloadsMetricsTotal Citations101Total Downloads592Last 12 Months50Last 6 weeks13 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

article Free Access Share on Implementation of precise interrupts in pipelined processors Authors: James E. Smith Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, WI Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, WIView Profile , Andrew R. Pleszkun Computer Sciences Department, University of Wisconsin-Madison, Madison, WI Computer Sciences Department, University of Wisconsin-Madison, Madison, WIView Profile Authors Info & Claims ACM SIGARCH Computer Architecture NewsVolume 13Issue 3June 1985 pp 36–44https://doi.org/10.1145/327070.327125Published:01 June 1985Publication History 158citation1,608DownloadsMetricsTotal Citations158Total Downloads1,608Last 12 Months185Last 6 weeks23 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF