This paper discusses interconnect capacitance extraction for system LCD circuits, where coupling capacitance is much significant since a ground plane locates far away unlike LSI interconnects. We focus on a pattern matching method with interpolation to implement an accurate and efficient capacitance extraction system, and present good implementations that are suitable for system LCD circuits. To reduce computational cost, interconnect structures are spatially divided into several sub-regions considering capacitance coupling range, and analyzed in each sub-region using a capacitance database pre-characterized by a 3-D field solver. This paper evaluates tradeoff curves between characterization cost and extraction accuracy for four division methods in lattice structures that are basic and common structures in LCD driver circuits. Experimental results reveal efficient division methods for accurate capacitance extraction.

This paper devises a real-time face object extraction algorithm for moving pictures. Considering that most of the existing object extraction algorithms are of too intensive computational complexity to enable the real-time execution that is applied to mobile video phone run on an embedded processor, this algorithm intends not only to reduce the computational complexity by employing modified snake but also to improve the precision of extracting pixels by an efficient estimation mechanism of the skin color portion within a face object. Simulation results demonstrate that by this algorithm QCIF 15fps is processed on a StrongARM processor in real-time.

A cipher core has been implemented, which is dedicated to a 64-bit block, 128-bit key, dynamically reconfigurable hardware-based cipher, called "Chameleon", in which two 32-cell, 8-context dynamically reconfigurable hardware units are employed to generate new subkeys for each of the 16 iterations in the encryption/decryption process. The proposed architecture has been implemented by 0.6 um CMOS3LM technology, using 65.6K transistors and attaining a maximum throughput of 317.5 Mbps. The new approach demonstrates distinctive features of enhanced complexity and flexibility dedicatedly for embedded encryption/decryption applications in the mobile computing.

In this paper, the VLSI implementation of a real-time EZW video coder is presented. The proposed architecture adopts a modified 2-D DWT subband decomposition scheme, with the purpose of reducing the transposition memory requirements of 2-D DWT. In addition, through the use of a parallelized partial zerotree EZW scheme, temporary buffer requirements between the DWT and EZW modules are also reduced. The video encoder is integrated in a 0.35 um 3LM chip by using 341 K transistors on a 4.93 x 4.93 mm2 die.

This paper evaluates the code efficiency of the ARM, Java, and x86 instruction sets by compiling the SPEC CPU95/ CPU2000/JVM98 and CaffeineMark benchmarks, in terms of code sizes, basic block sizes, instruction distributions, and average instruction lengths.

Abstract| An array cell (AC) architecture for the la y out design is described, whic h is dedicated to lowpow er design b y means of the NMOS 4-phase dynamic logic.An AC is constructed of (M2N)+2 transistors so as to constitute each t ype of NMOS 4-phase logic gates.A graph theoretic approach is exploited in the la y out design to reduce the la y out area.A n umber of experimental results demonstrate the practicability o f the proposed approach.

The architecture of a real-time wavelet video coder is described, with the main emphasis put on the memory bandwidth reduction and efficient VLSI implementation. The proposed architecture adopts a modified 2D subband decomposition scheme, along with a parallelized pipelined embedded zerotree wavelet coder architecture. The video encoder is integrated in a 0.35 /spl mu/m 3LM chip by using 341000 transistors on a 4.93/spl times/4.93 mm/sup 2/ die, which can process 720/spl times/480 30 fps pictures in real-time.

An architecture of a matrix-vector multiplier (MVM) is devised, which is dedicated to MPEG-4 natural/synthetic video decoding. The MVM can perform the matrix-vector multiplication both in the inverse discrete cosine transform (IDCT) and in the geometrical transformation of three-dimensional computer graphics (3-D CG); or, specifically, it can achieve the multiplication of a 4/spl times/4 matrix by a four-tuple vector necessary in the one-dimensional IDCT for eight pixels and in the geometrical transformation for a point in a 3-D space. This paper describes a new architecture of this MVM and also shows the implementation result of a functional module composed of four MVMs with the use of 440-k transistors, which can operate at 20 MHz or less.

A VLSI implementation of the H.324 audiovisual codec is described. A number of sophisticated low-power architectures have been devised dedicatedly for the mobile use. A set of specific functional units, each corresponding to a process of H.263 video codec, is employed to lighten different performance bottlenecks. A compact DSP core composed of two MAC units is used for both ACELP and MP-MLQ coding schemes of the G.723.1 speech codec. The proposed audiovisual codec core has been implemented by using 0.35 /spl mu/m CMOS 4LM technology, which contains totally 420 K transistors with the dissipation of 224.32 mW from single 3.3 V supply.

An adaptive quantization algorithm for MPEG-2 video coding using a neural network is presented in this paper. The proposed algorithm uses a backpropagation neural network to divide the macroblock activity into one of four categories: flat, edge, texture, fine-texture, and thus the macroblock can be quantized adaptively according to the human vision system (HVS) sensitivity. Experimental results show that this method can reduce block artifacts of flat area and distortion at edge effectively. Meanwhile, the picture subjective quality and objective quality of each frame are improved.

A VLSI implementation of a low-power DSP is described, which is dedicated to the G.723.1 low bitrate speech codec. A number of sophisticated DSP microarchitectures are devised mainly on dual multiply accumulators, rounding and saturation mechanisms, and two-banked on-chip memory. The proposed DSP architecture has been integrated in a total area of 7.75 mm/sup 2/ by using a 0.35 /spl mu/m CMOS technology, which can operate at 10 MHz with the dissipation of 45 mW from a single 3 V supply.

A layout approach is described dedicatedly for MMICs, in which layout elements are transistors, inductors, capacitors, resistors, coplanar-waveguides, etc., implemented by GaAs fabrication process. The layout issue typical of such MMICs consists essentially in how to realize a single-layered placement of different shapes of layout elements under a variety of spacing and orientating constraints as well as shaping variations. In this paper, the interconnection requirements among the elements are represented by a graph, to which a planarization algorithm is effectively applied. On the basis of the planarization result, the physical placement is first constructed with the use of a merging scheme and then refined iteratively by means of a new rectangle-packing algorithm. Experimental results are also shown to demonstrate the practicability of the described layout approach.

A layout approach for monolithic microwave integrated circuits (MMICs) is described, in which layout elements are transistors, inductors, capacitors, resistors, coplanar waveguides, etc., implemented in a GaAs fabrication process. The layout issue typical of such MMIC's consists essentially in how to realize a single-layered placement of different shapes of layout elements under a variety of spacing and orienting constraints as well as shape variations. In this paper, the interconnection requirements among the elements are represented by a graph, to which a planarization algorithm is applied. On the basis of the planarization result, the physical placement is first constructed with the use of a merging scheme and then refined iteratively by means of a new rectangle-packing algorithm. Experimental results are also shown to demonstrate the practicability of the described layout approach.

A digital filter is one of the fundamental elements in the digital video transmission, and a multiplier acts as the key factor that determines the operation speed and silicon area of the filter. Even though the coefficients to the filter are desired to be programmable, it is possible to change coefficients in the vertical fly-back interval of television receivers. This allows the preloadability of coefficients to the filter such that each coefficient can be treated as a constant during the filtering operation. Motivated by such functionalities, a novel multiplier together with an FIR filter architecture is described, which has been designed by means of a 0.5 /spl mu/m double metal CMOS technology.

Article Free Access Share on Low-power H.263 video CoDec dedicated to mobile computing Authors: Morgan H. Miki Dept. Information Systems Engineering, Osaka University Dept. Information Systems Engineering, Osaka UniversityView Profile , Gen Fujita Dept. Information Systems Engineering, Osaka University Dept. Information Systems Engineering, Osaka UniversityView Profile , Takao Onoye Dept. Information Systems Engineering, Osaka University Dept. Information Systems Engineering, Osaka UniversityView Profile , Isao Shirakawa Dept. Information Systems Engineering, Osaka University Dept. Information Systems Engineering, Osaka UniversityView Profile Authors Info & Claims ISLPED '97: Proceedings of the 1997 international symposium on Low power electronics and designAugust 1997 Pages 80–83https://doi.org/10.1145/263272.263288Published:01 August 1997Publication History 1citation333DownloadsMetricsTotal Citations1Total Downloads333Last 12 Months5Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A high performance and low power architecture is devised for a 4 Mbps infrared wireless communication system dedicated to mobile computing. In this architecture 4PPM (4-Pulse Position Modulation) infrared signals detected by an infrared receiver are digitized into TTL interface level pulses, and the digitized pulses are demodulated by a 1-bit digital demodulator. To extend the range of the link length, a 4PPM demodulator is synthesized to implement a demodulation algorithm which is constructed so as to accommodate the output tolerance of the infrared receiver. A experimental results show that the proposed 4 Mbps infrared communication system can achieve an error free link in the range of 0-140 cm at power consumption of 245 mW and 65 mW for transmitting and receiving, respectively. The communication controller is integrated in a 0.6 /spl mu/m CMOS standard-cell chip, which contains 10,015 transistors on a 12 mm/sup 2/ die.

Article An object code compression approach to embedded processors Share on Authors: Yukihiro Yoshida Dept. Information Systems Engineering, Osaka University Dept. Information Systems Engineering, Osaka UniversityView Profile , Bao-Yu Song Dept. Information Systems Engineering, Osaka University Dept. Information Systems Engineering, Osaka UniversityView Profile , Hiroyuki Okuhata Dept. Information Systems Engineering, Osaka University Dept. Information Systems Engineering, Osaka UniversityView Profile , Takao Onoye Dept. Information Systems Engineering, Osaka University Dept. Information Systems Engineering, Osaka UniversityView Profile , Isao Shirakawa Dept. Information Systems Engineering, Osaka University Dept. Information Systems Engineering, Osaka UniversityView Profile Authors Info & Claims ISLPED '97: Proceedings of the 1997 international symposium on Low power electronics and designAugust 1997 Pages 265–268https://doi.org/10.1145/263272.263349Online:01 August 1997Publication History 62citation364DownloadsMetricsTotal Citations62Total Downloads364Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

When a fabrication process is renewed, of practical importance is how to make the best use of layout resources so far accumulated for old fabrication processes. The present paper describes an automatic recycling system for layout data once used dedicatedly for functional cells of the standard-cell level. The main process of this system is i) to transform given layout data into a layout description format expressed in parameters associated with shapes, sizes, and locations of layout elements, and then ii) to resynthesize an optimal layout in accordance with a new set of design rules by means of a graph theoretic linear programming approach. A part of implementation results is also shown.

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An MPEG2 video decoder core dedicated to MP@HL (Main Profile at High Level) images is described with the main theme focused on an inverse discrete cosine transformer and a motion compensator. By means of various novel architectures, the inverse discrete cosine transformer achieves a high throughput, and the motion compensator performs different types of picture prediction modes employed by the MPEG2 algorithm. The decoder core, implemented in the total chip area of 22.0 mm/sup 2/ by a 0.6-/spl mu/m triple-metal CMOS technology, processes a macroblock within 3.84 /spl mu/s, and therefore is capable of decoding HDTV (1920/spl times/1152 pels) images in real time.>

Multiple instruction execution is a major approach to designing high-performance processors. Superscalar and VLIW processor that utilize instruction level parallelism are usually focused on. On the other hand, the multithreaded processor can be expected to achieve a high degree of multiple instruction execution by utilizing coarse grain parallelism. Many computer graphics applications (such as the radiosity method and ray-tracing method) can be optimized by reorganizing the code to take advantage of coarse grain parallelism, but the degree of instruction level parallelism is not sufficient for a superscalar processor. Experimental result using the radiosity method shows that the 4-thread multithreaded processor achieves 2.9 times speedup over single thread, while the 4-issue superscalar processor manages around 1.5 times. By duplicating two kinds of function units, the performance of a multithreaded processor increases to 3.7 times, but the performance of a superscalar processor is saturated at around 1.5 times. Therefore, for computer graphics applications, the multithreaded processor is a better approach than the superscalar processor.>

This paper describes a new clustering approach for VLSI placement, which is based on a fractal dimension analysis for the topological structure of modules in a logic diagram. A distinctive feature of this approach is that the concept of a fractal dimension has been introduced into a logic diagram in such a way that clustering of modules is iterated while the fractal dimension of clustered modules remains in a prescribed range. A part of experimental results is also shown, which demonstrates that our clustering approach achieves better solutions than the conventional placement without clustering.>

A multimicrocomputer system is described, stressing mainly software and hardware architectures, which has been constructed mainly for image creation. This system is distinctive mainly in that (i) 64 unit computers are interconnected with a root computer, each of equal performance, such that a number of unit computers constitute a pipelined computer and such pipelined computers work in parallel, all controlled by the root computer, and (ii) an intercomputer memory swapping unit is introduced, which is to be linked with a pair of unit computers to transfer a great amount of data at a time from one to the other through the use of a bus exchange switch.

A rerouting scheme is described, which is incorporated into an existing automatic routing system for single-layer printed wiring boards (PWB's) and hybrid integrated circuits. This scheme is to strip and reroute portions of the current wire patterns so that not only incomplete from-to's can be interconnected by means of getting rid of blockages, but those conductor paths so far determined which form unnecessarily long detours can be improved. Several implementation results are also shown.

A global router for gate array LSI's is described, which is intended to perform an interaction between placement and routing such that the features of one may be incorporated into those of another. This router is to generate for each net an interconnection pattern of channel segments in such a unified way of taking all interrelated interconnection requirements into account at once. A main objective of the router is not only to minimize the maximum of the local routing densities but also to distribute all the wiring requirements over channels evenly, in order to attain 100-percent interconnections within a limited area. An implementation result of the router is also shown.

This paper deals with the layering problem of multilayer PWB wiring, associated with single-row routing. The problem to be considered is restricted to the special case of street capacities up to two in each layer, and it is reduced to a problem of the interval graph by relaxing some restrictions in the original problem. Then, a heuristic algorithm is proposed for this problem.

The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multiphase clocking system, and occupies ordinarily a considerable part of chip area. In this paper a layout system for this portion of an LSI chip is described, which is constructed on the basis of heuristics for a set of interrelated optimization problems. Implementation results of the layout system are also shown to reveal that the random logic portion can be realized in such an areas as comparable to one done by manual layout.

The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multi-phase clocking system, and occupies ordinarily a considerable part of chip area. In this paper, a layout system for this portion of an LSI is described, which is constructed on the basis of a set of optimization heuristics. Experimental results of the layout system are also shown so as to reveal that the random logic portion can be realized in much the same area as can be done by manual layout.

Thts paper deals wRh the problem of enumerating all the cutsets or all the s-t cutsets separatmg two spectfied verttces s and t m an undirected graph A vanety of approaches have been proposed for this problem, among which one based on the partmon era set of veruces rote two sets is the most effi¢ienL It is first shown that an algorithm of this type has time complexity O((n + m)(n -log2#)#), and two new algorithms with ume complexity O((n + m)O + I)) are then proposed One of these new algorithms has space complexity O(nZ), and the other has space complexity O(n + m), where n and m are the numbers of veraces and edges, respectively, and ta ts the number ofs-t cutsets m a given graph The results of some computatmnal experiments are also described.An mvest~gaUon ~s made of the extent to whtch the new algorithms are better, and how good the performance of the old algorithm is, especmlly when a given graph is "dense," t e, 2m/(n(n -1)) _> 0.4.

High-density packaging is one of the most urgent requirements in the design of digital systems. In the assembly of such systems, printed wiring boards (PWB's) are used very often to provide the necessary interconnection among circuit modules. Thus, methods to raise wirability of routers are continually under investigation.

The problem of generating all the maximal independent sets (or maximal cliques) of a given graph is fundamental in graph theory and is also one of the most important in terms of the application of graph theory. In this paper, we present a new efficient algorithm for generating all the maximal independent sets, for which processing time and memory space are bounded by $O(nm\mu)$ and $O(n+m)$, respectively, where n, m, and $\mu$ are the numbers of vertices, edges, and maximal independent sets of a graph.