Dynamic amplifiers are emerging as a popular alternative to conventional operational amplifiers due to their high power-efficiency, albeit at the cost of linearity performance. We describe a dynamic amplifier that achieves both good linearity and low power with the help of an analog linearization technique based on the cancellation of expanding and compressing non-linearities inherent in the input transistors. A linearized dynamic amplifier is designed based on this technique in the GobalFoundries 22nm FDSOI process, leveraging its back-gate biasing feature. Our simulations demonstrate a 22dB of improvement in THD while incurring an negligible power overhead. Additionally, we proposed and implemented a calibration method to automatically optimize the amplifier’s performance.

Design automation and optimization for analog integrated circuits (ICs) are challenging, especially for transistor sizing. Given certain design specifications and circuit topology, circuit designers need to size various components to achieve the desired performance, possibly involving many optimization iterations. Recently, reinforcement learning (RL) has been applied to optimize analog circuits. The trained RL agents can achieve very high sample efficiency over evolutionary-based algorithms. By using the ability of transfer learning, the trained agent can be applied to optimize the same circuit across different technology nodes and even the circuits with different topologies. However, a significant bottleneck in applying machine learning (ML) techniques to analog IC design is the non-disclosure agreement (NDA) of the process development kit (PDK), which makes reproducibility of the prior art a big challenge. This work presents an RL framework that leverages the open-source SKY130 PDK to address the limitation above. We apply a novel heterogeneous graph neural network (GNN) called relational graph convolutional network (RGCN) as the function approximator of RL to capture more topological information about a circuit. As a proof-of-concept, low-dropout voltage regulators (LDO) are optimized by our proposed RL circuit optimizer framework to show its feasibility, achieving promising results.

The continuous-time pipelined (CTP) ADC is an emerging architecture that can achieve a lower oversampling ratio than conventional CT$\Delta \Sigma$ADCs with an improved power efficiency. In this paper, a bandpass CTP ADC is introduced for the first time, which permits direct digitization of bandpass signal spectra with improved image rejection and blocker tolerance. We also present an example and novel tunable multi-band inductorless architecture with a third-order interstage residue-amplifying filter. Detailed design analysis and challengesarepresented, along with two practical design examples having a sampling frequency of 6 GHz and center frequencies of 1.5 GHz and 2.1 GHz, achieving a bandwidth of 300 MHz with SQNR of 85 dBFS and 69 dBFS, respectively.

This paper presents a single-ended, passive hybrid for a simultaneous bidirectional (SBD) die-to-die link. It provides a signal-to-interference ratio better than 20 dB at 10 GHz while consuming only 3.72% of the total power and is used in a split-termination SBD transceiver (TRX) with a transimpedance amplifier (TIA) as a driver, which improves signal integrity by minimizing signal reflections. Extracted simulations of the TRX in 16nm CMOS over a 5 mm die-to-die link demonstrate error-free communication at 32 Gbps (16 Gbps + 16 Gbps) with a power efficiency of 0.42 pJ/bit on a 0.9 V. supply.

Digitally modulating the injection point in an injection-locked ring oscillator (ILRO) allows it to simultaneously serve as both a multiphase generator and phase interpolator (PI) or phase rotator. The resulting mostly-digital architecture is compact and promises low power in nanoscale CMOS, making it suitable for multi-Gbps dense I/O applications. This paper describes design considerations for such time-modulated ILROs, including the tradeoffs associated with determining their injection strength, modulation frequency, and pattern. These tradeoffs are illustrated in the design of a 14GHz PI in a 16nm FinFET technology. The proposed PI time-modulates between four different injection points within a ring oscillator to generate 96 fine phase settings (6.6 bits resolution). Based on post-extracted layout simulations, the overall PI consumes 24.1mW and occupies an area of 0.0033 $\mathrm{mm}^{2}$. The locking range is 12.4 - 14.3GHz in the typical process corner. The simulated jitter is 592fs-rms (including thermal noise and determinstic jitter) while the PI is rotating at a 200ppm frequency offset from 14GHz. A novel linearity calibration mechanism is used to correct for systematic and random phase imbalances.

Continuous-time pipelined (CTP) ADCs have shown the potential to alleviate the challenges of discrete-time (DT) pipelined converters with Multi-GHz bandwidth, but have so far required an oversampling ratio (OSR) of at least 4. After elucidating the factors that limit CTP bandwidth, this paper presents a design methodology for near-Nyquist CTP ADCs. The delay circuit is optimized to match the ADC/DAC path in both its broadband magnitude response and phase. The residue filter response is optimized to prevent image signals from overloading the subsequent stage. We show that practical circuits can realize these optimized responses and extend the bandwidth of the CTP architecture to OSRs of 1.5-2.0, essentially equivalent to the OSR of DT converters when allowing for practical anti-aliasing. The direct path (i.e. delay) and the residue-amplifying filter circuits required for 3 GHz bandwidth are incorporated into a complete 4-bit 10 GS/s CTP ADC stage in a 28nm CMOS prototype. Simulation and measurement results confirm that CTP ADCs can operate at a near-Nyquist sampling rate with an OSR of 1.7.

Forward-error-correction (FEC) codes have become an integral part of high-speed wireline links. Signal-to-noise ratio, minimum mean-squared error, and pre-FEC BER are common performance metrics used to design and optimize link parameters, such as the tap coefficients in feed-forward and decision-feedback equalizers. This paper shows that the equalizer parameters found by conventional methods do not necessarily minimize post-FEC BER due to the unaccounted-for negative impact of DFE error propagation on FEC performance. However, the introduction of 1/(1+D) pre-coding eliminates long error bursts so that both pre-FEC and post-FEC BER are minimized with the same equalizer coefficients. These observations may have implications on the architecture and optimization of wireline transceivers.

This paper presents all-digital calibration algorithms for correcting static non-linearities in an ADC. A bit-by-bit (BB) calibration is proposed as an alternative to the existing radix calibration. The proposed calibration algorithm is initially demonstrated using a non-uniform ADC model generated in Matlab. A hybrid radix/bit-by-bit calibration is also developed to reduce the computational complexity of BB calibration. The calibration algorithms are then applied to measurement data from two different ADCs: a 6-bit folding-flash; and a 10-bit dual-split capacitor (DSC)-DAC SAR ADC. In both ADC architectures, the BB and hybrid calibrations outperform radix calibration. The BB calibration improved the SNDR and SFDR of the folding-flash ADC from 29.5 dB to 31.9 dB and 33.3 dB to 43.6 dB, respectively. Likewise, after applying the hybrid calibration on the DSC-DAC SAR ADC, the SNDR and SFDR improved from 31.8 dB to 47 dB and 33.6 dB to 58.9 dB, respectively. The hybrid calibration achieves performance similar to that of BB calibration while demonstrating a significant reduction in computational complexity.

For serial wireline communication beyond 56 Gb/s, bandwidth-efficient modulation is needed. Four-level pulse amplitude modulation (4-PAM) has become the standard technique at 56-64 and 112 Gb/s. However, whereas decision feedback equalization (DFE) with 5 taps or more was common for 2-PAM links at lower data rates, the speculative look-ahead techniques required to satisfy a DFE's timing requirements at 56 Gb/s increase power consumption exponentially with the number of taps and the number of modulation levels. Thus, 4-PAM DFEs at 56 Gb/s are generally limited to 2 taps or fewer. This limitation, in turn, necessitates the use of long (10 taps or more) finite impulse response (FIR) feed-forward equalization (FFE) to accurately eliminate the intersymbol interference in long reach (LR) channels. Thus, LR receivers at 56-64 and 112 Gb/s comprise an analog-to-digital converter (ADC) followed by digital equalization, and the transmitters increasingly use a digital-to-analog converter (DAC) preceded by a digital filter. Discrete multitone (DMT) signalling obviates the need for a long FIR FFE and DFE, and has demonstrated better spectral efficiency than 4-PAM above 50 Gb/s. In this work, we consider the potential of DMT for wireline communication beyond 100 Gb/s. For example, a spectral efficiency of 2.5 bits/sample is achievable over an IEEE P802.3ck channel with 18 dB loss at 40 GHz, affording an aggregate data rate of 200 Gb/s at 80 GS/s with 150 fs of jitter and 1.26 mV of noise at the input to the receiver. Significant improvement in bit error rate (BER) is obtained by increasing DAC resolution to 8 bits.

TDC specifications are critical determinants of the range, resolution, and accuracy of SPAD-based TCSPC 3D imaging systems. In particular, the TDC conversion time plays a vital role in emerging architectures wherein TDCs are shared across the sensor array. Here, a statistical analytical model is employed to relate the number of required TDCs per SPAD array to the 3D image accuracy and frame rate, taking into account environmental factors such as ambient light and distance. The model verifies that sharing schemes, contrary to TDC-per-SPAD scheme, can improve efficient use of area and power, and it also permits TDC sharing architectural exploration to determine the number of TDCs required for given array size. Monte Carlo numerical simulations verify the accuracy of the proposed method.

The optimization of a TCSPC system requires modeling which considers the design specifications and parameters of the target application under different operating scenarios. Since single-photon detection is fundamentally a stochastic process, extensive behavioral Monte Carlo simulations are normally used. Their accuracy depends upon computation time. However, the trend towards larger SPAD arrays and emerging complex TDC sharing architectures requires much faster simulation methods. In this paper, a simple, fast and accurate analytical model is presented to address this need. It accounts for dead time effects which result in missed photon counts through the analysis of inhomogeneous continuous time Markov chain. The effective received power and photon detection rate are determined and the corresponding analytical histogram is created. This histogram is the basis for calculating time of flight and can be used to explore architectural alternatives and accelerate design verification. Outputs of the presented analytical model match those of Monte Carlo simulations, and are produced considerably faster. The computation time improvement grows with array sizes and this enables parametric analysis of TCSPC system.

A low power integrating mixer successive approximation register (SAR) prototype chip for spectrum sensing is fabricated for portable transceivers targeting IEEE 802.22 cognitive radio applications. The integrating mixer SAR combines mixing, current-domain windowing, and integration to implement the short-time Fourier transform. Integration with programmable time constant is incorporated within the mixer by utilizing binary-weighted capacitive loads, which double as the sampling capacitors of a SAR ADC. The design operates over a frequency range of 0.05–1.25GHz, consumes 0.88mW from 1.1/1.2V supplies and obtains an average dynamic range (DR) of 25.7–27.9dB.

This paper presents an all-digital background calibration for timing mismatch in time-interleaved analog-to-digital converters (TI-ADCs). It combines digital adaptive timing mismatch estimation and digital derivative-based correction, achieving lower hardware cost and better suppression of timing mismatch tones than previous work. In addition, for the first time closed-form exact expressions for the signal-to-noise and distortion ratio (SNDR) of a four-channel TI-ADC with timing mismatch after derivative-based digital correction are obtained, which can be used to guide the design. Simulation results of a four-channel TI-ADC behavioral model and measurement results from a commercial 12-bit 3.6-GS/s two-channel TI-ADC show that the proposed all-digital calibration can accurately estimate the timing skew and effectively correct the timing mismatch errors, while also confirming the analytic SNDR expressions.

A highly digital phase lock loop with a multi-phase bang-bang phase detector is proposed to speed up lock time and to increase the pull in range. To reduce power consumption, the high speed counter and re-timing circuit in the feedback loop are disabled after frequency lock is achieved.

This paper analyzes the impact of clock skew between comparators in a flash ADC, showing that the SNDR penalty introduced by this effect can become significant at high frequencies. To address this issue, a passive resonant clock network is proposed to distribute the clock to the comparators in a flash ADC. The inductive termination of this network serves to resonate out the parasitic and input capacitances of the ADC, allowing for a 2.5-GHz clock signal to be conveyed to a load of 256 comparators while consuming less power than traditional clock networks due to the reduced number of active clock buffers required. This clock network produces little timing skew at the resonant frequency, thereby obviating the need for a track-and-hold amplifier, which further reduces the power requirements of the ADC. This clock network was implemented in a 5-bit flash ADC designed in 65 nm CMOS, with a measured SNDR of 26 dB.

This paper proposes a technique for characterization of the frequency-dependent losses in a wireline communications link. By using the measured jitter at the output of a receiver front-end as its only input, this method is able to estimate both the pulse response and frequency response of the link, including the effects of the transmitter output, the channel itself, and the receiver front-end. Simulated and measured results verify the accuracy of this technique, which can be used to efficiently adapt the settings of critical circuit blocks in the link, such as equalizer tap weights.

A broadband preamplifier with gain control and automated common-mode level regulation is presented. It is implemented in 65-nm CMOS as part of an analog front-end (AFE) that is especially suitable for wireline receivers incorporating digital signal processing or multilevel modulation. S-parameter measurements of the receiver show that the preamplifier remains well matched to the channel impedance across all gain settings with an S11of less than -8 dB to frequencies beyond 25 GHz. The measured S21of the receiver shows that the preamplifier is capable of achieving 10 dB of gain control. The preamplifier alone consumes from 16.7 mA to 56.7 mA from a 1.2 V supply, depending on its gain setting.

By splitting the input sampling capacitor of a SigmaDelta modulator into several time-interleaved branches, FIR filtering can be incorporated into the signal transfer function. Doing so imposes little or no overhead in the design of the opamps. Simulations of a 3rd-order modulator demonstrate that up to 65 dB of anti-aliasing can be obtained with 5 time-interleaved switched capacitor branches.

This paper presents a passive Alter for the front end of a high speed serial link receiver to aid timing recovery. The Alter provides simultaneous lowpass and highpass transfer characteristics to generate the data and its slope respectively. Slope detection is demonstrated at 10-Gb/s. As a proof of concept, the Alter was used to extract a 2-GHz clock from a 2-Gb/s 231- 1 random data sequence based on a modified minimum mean squared error (MMSE) criterion. The circuit is fabricated in a 0.18 mum CMOS process and consumes 21.6 mW from a 1.8 V supply.

Crosstalk and inter-symbol interference are major obstacles towards increasing the data rate of chip-to-chip links. They are especially important in long, single-ended, parallel links. We find that when crosstalk is the dominant source of received noise, a transmitted pulse shape that combines slew-rate limiting with transmitter pre-emphasis is preferred. We present a framework for choosing a transmit pulse-shape that minimizes the combined effects of both crosstalk and inter-symbol interference. When implementing this optimal pulse shape, filter taps that are fractionally spaced are beneficial. As a test, various pulse shapes were injected into a test channel with three parallel microstrip lines, and the received eye diagrams were measured. The crosstalk-aware pulse shape results in an increased eye opening when compared to square and pre-emphasis pulses

We propose a bit-serial LDPC decoding scheme to reduce interconnect complexity in fully-parallel low-density parity-check decoders. Bit-serial decoding also facilitates efficient implementation of wordlength-programmable LDPC decoding which is essential for gear shift decoding. To simplify the implementation of bit-serial decoding we propose a new approximation to the check update function in the min-sum decoding algorithm. The new check update rule computes only the absolute minimum and applies a correction to outgoing messages if required. We present a 650-Mbps bit-serial (480, 355) RS-based LDPC decoder implemented on a single Altera Stratix EP1S80 FPGA device. To our knowledge, this is the fastest FPGA-based LDPC decoder reported in the literature