Electric Encoders (EEs) are extensively used for position measurement in precise motion control. They are characterized by high resolution and simple circuit interface. Some EEs gauge the angle value exploiting a combination of coarse and fine measures. In both cases the outputs are the sine and cosine of angle. In this context the most delicate operation regards the measurement of initial angle, corresponding to the absolute position of EE. In some commercial systems the process for absolute position computation is based on an M-N algorithm, which has limitations in terms of hardware and flexibility because uses memory. In this paper, a new method based on Chinese Remainder Theorem (CRT) is proposed for absolute position computation. This method is based on Residue Number System (RNS) and has advantages in terms of hardware and flexibility because doesnt use memories. For this reason, the same hardware can be used with different EEs just changing the value of few registers.

In this paper the problem of error detection in elliptic curve point multiplication is faced. Elliptic Curve Point Multiplication is often used to design cryptographic algorithms that use fewer bits than other methods with the same security level. One of the mode used to break the security of cryptosystem is the injection of a fault in the hardware realizing the cryptographic algorithm. Therefore, to avoid this kind of attack, is very important to develop cryptosystems that are able to detect errors induced by a fault. The paper takes into account the algorithm for elliptic Curve Point Multiplication based on a sequence of additions called ldquoaddition chainrdquo and shows how suitable modifications of the algorithms used for computing the point multiplication adds the error detection property to the algorithm.

Processing performance of algorithms implemented on conventional processors or DSP can degrade when bit level operations are involved. This degradation is related to the characteristics of logic and arithmetic operators present inside the processors, that are optimized for word level operations. Different methods have been proposed for overcoming this problem. A very interesting method is based on the introduction of specific logic and arithmetic units, jointly to the conventional integer or floating-point units. Due to the great variability of the bit level operations that must be performed, a fixed structure unit is not very suitable for this application. This fact has suggested the introduction of units based on arrays of reconfigurable cells, as the RAM based Look-up Tables. In this paper an alternative reconfigurable cell, specialized for the realization of bit manipulating unit, is described and evaluated. The comparison results show that the proposed solution is very efficient in terms of number of transistors (or silicon area) if compared to a conventional approach based on Look-up Table.

In previous works ([1], [2] and [3]) the authors presented ADAPTO (Adder-based Dynamic Architecture for Processing Tailored Operators), a Reconfigurable Functional Unit (RFU) that accelerates computations on data of shorter size than the native processor wordlength. ADAPTO is a reconfigurable array inserted directly in the data-path of the microprocessor in order to reduce the communication overhead between the reconfigurable unit and the microprocessor. An important feature of ADAPTO is the capacity to reconfigure itself and execute operations in one clock cycle. ADAPTO, differently from other architectures presented in the literature ([6] [7]) is based on Full-Adders (FA) instead of LUTs. The FA can be configured to perform logical and arithmetical operations with the advantage of a less number of transistors than in the case of a LUT approach. In this paper we show how ADAPTO increases the performance of a RISC processor in the executions of algorithm processing short size data.

Existing triode models don't behave well especially when grid current flows so that simulation results are not reliable if the device operates in that region. Moreover, even in absence of grid current, averaged output characteristics could be better reproduced. We present a new approach to create customized models, especially if some physical parameters are not known, as it usually happens.

In this paper, the design of a finite impulse response (FIR) filter with fault tolerant capabilities based on the residue number system is analyzed. Differently from other approaches that use RNS, the filter implementation is fault tolerant not only with respect to a fault inside the RNS moduli, but also in the reverse converter. An architecture allowing fault masking in the overall RNS FIR filter is presented. It avoids the use of a trivial triple modular redundancy (TMR) to protect the blocks that performs the final stages of the RNS based FIR computation.

Low cost microprocessors and DSPs are optimized to perform general arithmetic and logic operations on native wordlength. On the other hand, the efficiency decreases when they process shorter data (more clock cycles per operation are required). Recently different solutions have been proposed to overcome this problem. Among those, the one based on a main processor with a Reconfigurable Unit (RU) used as coprocessor (to speed up fine grained operations) is the most common. Typically those coprocessors, similar to FPGA, are composed by Look-Up Tables (LUTs) and pass transistors interconnects. In this way, due to the great number of reconfiguration bits, it is impossible to obtain together a run-time reconfiguration and an efficient implementation, avoiding idle hardware resources . This paper proposes a new dynamic reconfigurable architecture that can be embedded in microprocessors or low cost DSPs to accelerate the execution of the above mentioned operations. The goal of ADAPTO (Adder-based Dynamic Architecture for Processing Tailored Operators) is to reduce the hardware complexity and the reconfiguration time, with respect to typical LUT based Reconfigurable array. ADAPTO supports both hardware reconfiguration and instruction execution in the same processor clock cycle. This goal has been obtained by using a new reconfigurable unit based on full adders, instead LUTs, and simplifying the network interconnect.

This paper shows how the use of exhaustive fault injection campaigns in conjunction with the analysis of the property of a circuit, allows to improve the efficiency of the checker of self checking circuits. Experimental results coming from fault injection campaigns on a Reed-Solomon decoder demonstrated that by observing the occurred errors and the correspondent detection module has been possible to reduce the number of detection module, while paying a small reduction of the percentage of SEUs that can be detected.

In this paper a low-power implementation of an adaptive FIR filter is presented. The filter is designed to meet the constraints of channel equalization for fixed wireless communications that typically requires a large number of taps, but a serial updating of the filter coefficients, based on the least mean squares (LMS) algorithm, is allowed. Previous work showed that the use of the residue number system (RNS) for the variable FIR filter grants advantages both in area and power consumption. On the other hand, the use of a binary serial implementation of the adaptation algorithm eliminates the need for complex scaling circuits in RNS. The advantages in terms of area and speed of the presented filter, with respect to its two's complement counterpart, are evaluated for implementations in standard cells.

Reed Solomon (RS) codes are widely used to protect information from errors in transmission and storage systems. Most of the RS codes are based on GF(28) Galois Fields and use a byte to encode a symbol providing codewords up to 255 symbols. Codewords with more than 255 symbols can be obtained by using GF(2m) Galois fields with m > 8, but this choice increases the complexity of the encoding and decoding algorithms. This limitation can be superseded by introducing parity sharing (PS) RS codes that are characterized by a greater flexibility in terms of design parameters. Consequently, a designer can choose between different PS code implementations in order to meet requirements such as bit error rate (BER), hardware complexity, speed, and throughput. This paper analyzes the performance of PS codes in terms of BER with respect to the code parameters, taking into account either random error or erasure rates as two independent probabilities. This approach provides an evaluation that is independent of the communication channel characteristics and extends the results to memory systems in which permanent faults and transient faults can be modeled, respectively, as erasures and random errors. The paper also provides hardware implementations of the PS encoder and decoder and discusses their performances in terms of hardware complexity, speed, and throughput.

Reed-Solomon (RS) codes are widely used to identify and correct errors in transmission and storage systems. When RS codes are used for high reliable systems, the designer should also take into account the occurrence of faults in the encoder and decoder subsystems. In this paper, self-checking RS encoder and decoder architectures are presented. The RS encoder architecture exploits some properties of the arithmetic operations in GF(2m). These properties are related to the parity of the binary representation of the elements of the Galois field. In the RS decoder, the implicit redundancy of the received codeword, under suitable assumptions explained in this paper, allows implementing concurrent error detection schemes useful for a wide range of different decoding algorithms with no intervention on the decoder architecture. Moreover, performances in terms of area and delay overhead for the proposed circuits are presented.

It is widely known that an adder can be checked by using check symbols that are residues of the numbers modulo some base. This paper extends this characteristic to a radix r signed digit (SD) representation. The confinement of the carry operation can also be exploited to localize the faulty resources in the SD adder and to reconfigure the adder in order to work with a reduced dynamic range. The fault localization procedure is presented in this paper and the reconfiguration the SD adder after the fault localization is discussed

Reed Solomon codes are widely used to identify and correct data errors in transmission and storage systems. When Reed Solomon (RS) codes are used for high reliable systems, the designer should take into account also for the occurrence of faults in the encoder and decoder blocks. In this paper a method to obtain a self-checking RS decoder is presented and different architectures for its implementation based on concurrent error detection are provided. The proposed method can be used for a wide range of different decoder algorithms with no intervention on the decoder architecture

This paper proposes a methodology for the development of fault tolerant arithmetic circuits using an r-radix signed digit (SD) representation. A residue checking based technique is applied to detect errors caused by faults belonging to the considered stuck-at fault set. We developed a technique to detect the presence of a fault in the adder by using a completely independent circuit that uses check symbols that are residues of the numbers modulo a suitable base. We show that for any radix r > 3 the correctness of the adder operation can be checked simply by using two check symbols. This property is used to extend the fault detection also to SD constant multipliers and to the rounding operation. The extension to SD constant multiplier can be easily obtained by implementing the multipliers using a shift and add architecture. For the truncation operation we notice that many error detection techniques based on some arithmetic properties of the circuits fails when the truncation operation is performed. Instead, we show how our method can be applied to this operation with low area overhead and therefore it is useful to implement self-checking finite impulse response (FIR) filters

In this paper the implementation of a multirate QPSK modulator is presented. The modulator architecture has been optimized to reduce the hardware complexity and maximize the carrier frequency in order to meet the requirements of deep space and satellite applications. Finally, the performance has been evaluated by implementing the modulator on a Xilinx XC2V3000 FPGA

In this paper, a methodology for the development of fault-tolerant adders based on the radix 2 signed digit (SD) representation is presented. The use of a number representation characterized by a carry propagation confined to neighbor digits implies interesting advantages in terms of error detection, fault localization, and repair. Errors caused by faults belonging to a considered stuck-at fault set can be detected by a parity-based technique. In fact, a carry-free adder preserving the parity of the augends can be implemented allowing fault detection by using a parity checker. Regarding fault localization, the "carry-free" property of the adder ensures the confinement of the error due to a permanent fault to only few digits. The detection of the faulty digit has been obtained by using a recomputation with shifted operands method. Finally, after the fault localization, graceful degradation of the system intended as the reduction of the performances versus a correct output computation can be obtained by using two different procedures. The first one allows obtaining the correct output by recomputing the result performing two different shift operations and using the intersection of the obtained results to recover the correct output, while the second one is based on a reduced dynamic range approach, which allows us to obtain the result in only one step, but with fewer output digits.

In this paper, an innovative self-checking Reed Solomon encoder architecture is described. The presented architecture exploits some properties of the arithmetic operations in GF(2/sup 3/) related to the parity of the binary representation of the field elements. Moreover, a method for introducing self-checking capabilities on all the arithmetic structures used in the Reed Solomon encoder is presented. Finally the self-checking encoder architecture has been mapped on a FPGA evaluating its area overhead.

This paper describes a novel architecture of fault tolerant solid state mass memory (SSMM) for satellite applications. Mass memories with low-latency time, high throughput, and storage capabilities cannot be easily implemented using space qualified components, due to the inevitable technological delay of these kind of components. For this reason, the choice of commercial off the shelf (COTS) components is mandatory for this application. Therefore, the design of an electronic system for space applications, based on commercial components, must match the reliability requirements using system level methodologies. In the proposed architecture, error-correcting codes are used to strengthen the commercial dynamic random access memory (DRAM) chips, while the system controller is developed by applying fault tolerant design solutions. The main features of the SSMM are the dynamic reconfiguration capability, and the high performances which can be gracefully reduced in case of permanent faults, maintaining part of the system functionality. The paper shows the system design methodology, the architecture, and the simulation results of the SSMM. The properties of the building blocks are described in detail both in their functionality and fault tolerant capabilities. A detailed analysis of the system reliability and data integrity is reported. The graceful degradation capability of our system allows different levels of acceptable performances, in terms of active I/O link interfaces and storage capability. The results also show that the overall reliability of the SSMM is almost the same using different RS coding schemes, allowing a dynamic reconfiguration of the coding to reduce the latency (shorter codewords), or to improve the data integrity (longer codewords). The use of a scrubbing technique can be useful if a high SEU rate is expected, or if the data must be stored for a long period in the SSMM. The reported simulations show the behavior of the SSMM in presence of permanent and transient faults. In fact, we show that the SCU is able to recover from transient faults. On the other hand, using a spare microcontroller also hard faults can be tolerated. The distributed file system confines the unrecoverable fault effects only in a single I/O Interface. In this way, the SSMM maintains its capability to store and read data. The proposed system allows obtaining SSMM characterized by high reliability and high speed due the intrinsic parallelism of the switching matrix.

In this paper a novel bacterial algorithm to extract the rule base starting from a training set is presented. The proposed algorithm also optimizes the input and output membership function parameters. The algorithm is based on the use of bacterial operations on every rule in the rule set. A reduced optimized rule base is obtained by using rule fusion and removal procedures. The algorithm performance was evaluated by using a six input variables target function frequently used in the literature as benchmark. The obtained results show good performance with respect to the works recently presented in the literature.

The use of Commercial Off The Shelf (COTS) devices for space applications is growing due the higher cost and lower performance of corresponding dedicated devices. The needed reliability is achieved at the architectural level. This paper faces this problem in the design of a Solid State Mass Memory (SSMM). High-energy particles induce soft and hard errors in DRAMs devices. In our approach, these errors are mitigated at system level rather than at device level. In particular our SSMM is based on a suitable Error Control Code (ECC) and on memory redundancy in order to improve the tolerance with respect to DRAM induced errors. Accurate space environment models and decisional models are important to optimize the SSMM overhead, the amount of radiation shielding, the overall mass, and could suggest, if possible, the selection of a better orbit with a more benign environment. In this paper we describe the methodology used to select the parameter design for a class of memory architectures.

In this paper an extensive comparison among alternative algorithms for the implementation of a digital demultiplexer has been carried out. The computational complexity, the performances and the accuracy with respect to the quantization noise effects have been evaluated for the different algorithms. In particular, the digital architecture has been designed to replace an analog filter bank composed of six surface acoustic wave (SAW) devices. This implementation is used, at present, by Alenia Space Division in the Eutelsat Hot-Bird satellites. The obtained digital architecture has been mapped on six Altera Flex 10K-100 devices. The final test bed, that includes a complete interface to the Alenia demodulator, has been implemented on a four-layers PCB.

The new portable multimedia systems are characterized by very low-power absorption, very high throughput, high complexity and shortened time to market. In this kind of application, besides standard DSP techniques, Intelligent Techniques(IT) such as Fuzzy Logic and Neural Networks, are gaining more and more importance. This fact leads to the development of new CAD tools for the optimization of the overall IT design process. In this paper, a CAD environment named FSDT (Fuzzy System Development Tool) is described. FSDT supports the different phases of the development process namely optimization, simulation and code generation either for software (C or Assembler) or hardware (Verilog) implementations of Multiple Input Multiple Output (MIMO) fuzzy inference processors. FSDT has been written in C++ and, at present, an implementation interfaced with Matlab is available. A new implementation based on Ptolemy (a simulation engine, developed at the University of California at Berkeley) is under development.

Unconventional number systems have been proposed as an alternative to conventional weighted number systems in realizing digital signal processing (DSP) processors. A well-known advantage of these systems is related to the intrinsic property of performing operations in a finite field of numbers, thus always avoiding overflow. This advantage is fully met by applying the proposed method, which realizes a full parallel linear combinator as a single device by the residue number system (RNS) approach. The linear combinator is implemented as two parallel modular structures which can work very quickly by means the well-known isomorphism technique. This technique reduces the computational costs of multipliers to that of adders. Some particular aspects of VLSI implementation are also discussed.>

The authors propose a residue number system (RNS) architecture that realizes fast division. This architecture is fully developed in the particular case of eight-bit wordlength; in this case significant simplifications are reached. The whole divider appears as a combinatorial structure. A layout of the proposed architecture has been realized in a 1.5- mu m CMOS technology, SPICE simulation of the circuit extracted from this layout has shown the overall propagation time in performing the division to be about 100 ns.>

A novel approach to the definition of the roots of unity in the RNS (residue number system) is presented. The definition is based on a suitable polar representation of the complex residues. The resulting RNS Fourier transform provides an algorithm for performing circular convolutions characterized by flexibility in terms of length, computational cost, and storage.>