AMD had previously detailed its exascale research journey from initial targets and requirements to the development and evolution of its vision of a high-performance computing (HPC) accelerated processing unit (APU), dubbed the Exascale Heterogeneous Processor or EHP. At the conclusion of that work, the learnings were integrated into the design of the node architecture that went into the Frontier supercomputer, the world’s first exascale machine. However, while the Frontier node architecture embodied many of the attributes of the EHP concept, advanced heterogeneous integration capabilities at the time were not yet sufficiently mature to realize our vision of a fully-integrated APU for HPC and AI. In this paper, we finish the EHP’s story by digging deeper into why an APU was not the right solution at the time of our first exascale architecture, what the shortcomings were of previous EHP concepts, and how AMD further evolved the concept into the AMD Instinct™ MI300A APU. MI300A is the culmination of years of AMD developments in advanced packaging technologies, its APU hardware and software, and the next step in our highly effective chiplet strategy to not only deliver a groundbreaking design for exascale computing, but to also meet the demands of new large-language model and generative AI applications.

Noise introduced on the supply networks by simultaneous switching of the nodes of complex macros is becoming an important issue in very deep sub-micron technologies. Server-class microprocessors demand design of very high speed multiported macros that generate high peak currents and current slew-rates. This paper investigates one such macro: a fully-associative, multiported data TLB. Our simulations show a slowdown of 10-20% due to the supply noise despite robust C4-based supply network. The traditional solution of employing decoupling capacitors to combat the supply noise results in an unacceptable area increase. Macro design techniques that can reduce peak current and current slew rate without reducing the speed of critical path are proposed. Employment of hierarchical match line and delayed split precharge techniques reduce the SSN and the required decoupling capacitance by a factor of 5x.