This paper analyses the phase performance of a RX front-end architecture implemented in a 65-nm CMOS process for linear phased arrays at 24 GHz. The front-end is based on an array of LNAs and phase shifters, which can be used in analog and hybrid beamformers. The penalties of the radiation pattern are associated with metrics calculated from the phase performance. PVT variations and mismatch have been included. Results show that the front-end could potentially attain, in spite of PVT variations, a value near the defined by the mismatch.

This paper presents the design of a differential quadrature all-pass filter as a quadrature generator for being used in a phase shifter operating at 19.5 GHz, employing 65 nm CMOS technology. Various solutions have been investigated to address errors occurring in the phase and magnitude of I/Q signals at the output of the quadrature all-pass filter when connected to the next stage. The best result is obtained when combining asymmetry of the network with the inclusion of two additional resistive elements, achieving a quadrature error lower than$2.0^{\circ}$and a magnitude error lower than of 0.17 from 17 GHz to 22 GHz at the output of the quadrature all-pass filter. As an application, it has been proven that the RMS phase error at the output of a 5-bit active phase shifter has been decreased from$7.6^{\circ}$to$2.3^{\circ}$.

This paper presents a study of the frequency response of a low noise amplifier designed with an inductorless technique, in which an auxiliary amplifier boosts the transconductance of a common-gate stage. The circuit aims to work at the FR1 band (< 6 GHz). The analysis is centered on the modeling of the frequency response of the LNA by assuming a dominant pole in the boosting amplifier. The subsequent second-order system fits the dependence of the simulation results; however, the inclusion of a third pole matches the simulation results accurately.

Passive Polyphase Filters (PPF) are extensively used in analog signal processing system which work with quadrature signals, either filtering or generating it. However, the quality of PPF performance in these kinds of operation rely on a perfect matching in components and a symmetrical topology. Thus, mismatch effects could produce notable degradation in PPF response. Despite this, mismatch impact in PPF has not been thoroughly analyzed previously in literature to the best of authors knowledge. In this work, a systematic method is proposed to search the worst possible mismatch in a PPF with any number of stages for a certain tolerance. Then, for the 1-stage case, both PPF types (I and II) are analyzed to evaluate how this non-ideality alters the response of this kind of filters.

This paper presents a new analog front-end for short-reach high-speed optical communications. It compensates the limited bandwidth of SI-POF transmission systems. In particular, the front end has been designed using a cost-effective 0.18-µm CMOS technology and fed with only 1V. The proposed architecture, formed by a transimpedance amplifier and a continuous-time equalizer, targets 1.25 Gb/s transmission for a simple NRZ modulation in an optical link composed of 50 m of SI-POF and a large area Si PIN photodetector.

In this paper, a 3.125 GHz four stage voltage controlled ring oscillator is presented. The oscillator has been designed in a 0.18 μm CMOS process with a 1.8 V supply. Behavioural simulations predict an 18% tuning range for the oscillator, with a -91 dBc/Hz phase noise at a 1 MHz offset. Its power consumption has been simulated to be only 12.6 mW.

This paper presents a new transimpedance amplifier (TIA) for 2.5 Gbit/s optical communications realized in a standard 90 nm CMOS process. The proposed TIA is based on a conventional structure with an inverting voltage amplifier and a feedback resistor, but incorporates a new technique to enhance the input dynamic range and to prevent the TIA saturation at high input currents. Post-layout results show an optical sensitivity of -30 dBm for a BER=10-12and a maximum input current of 1 mApp, what leads to an optical power dynamic range above 27 dB. The power consumption of the TIA is only 4.3 mW at a single supply voltage of 1 V.

This work introduces a monolithic 10GBase-LX4 limiting amplifier in a low-cost 0.18 µm CMOS digital process intended for optical fiber communications. The proposed configuration includes two inductorless frequency compensated voltage amplifiers. The topology also incorporates a conventional RC network in order to avoid drifts due to matching and temperature between −20 and 80 °C. This circuit presents a 200 kHz lower cut-off frequency and a 3.5 GHz higher cut-off frequency with 32 dB gain.