This paper presents a low-power, 360° active LC phase shifter with an amplitude control mechanism. The proposed design employs a phase selection technique that includes a compact, ring-oscillator-based quadrature phase generator and automatic amplitude control, enabling full phase range coverage with consistent amplitude. The circuit was designed, laid out, and extracted in a 22-nm fully depleted SOI (FD-SOI) process. Operating within an 8–12GHz frequency range, the injection-locked quadrature phase generator and phase shifter consume between 3.5 and 5mW.

In this paper, we present a novel 2-Megabit (Mb) In-Memory Computing (IMC) architecture using advanced Voltage-Gated Spin-Orbit Torque (VGSOT) MRAM. This architecture is designed with 22nm FDSOI technology, and it offers nonvolatile storage, logic operations including AND, NAND, OR, NOR operations, and in-memory dot products for binary neural networks (BNNs). The compact IMC 3T1R bit-cell occupies 0.149 µm2, achieving high write and read speeds of 250-MHz and 1.72-GHz, respectively. Using a BNN model architecture comprising 784 neurons in the input layer, 512 neurons in the hidden layer, and 10 neurons in the output layer, impressive inference accuracies of 95.04% and 84.59% have been achieved when assessing the MNIST and FMNIST datasets, respectively. The proposed VGSOT MRAM architecture’s bit-cell area, read, and write power is 73.34%, 88.82%, and 38.78% less than 2T1R SOT-MRAM respectively.

The CMOS switched-capacitor power amplifier (SCPA) proposed in 2011 [1]-[2] achieved much higher system efficiency than conventional transmitter architectures. In this paper, SCPA linearity is also analyzed and improved with new techniques. Specifically, a baseband harmonic-rejection (BBHR) technique is used to minimize the counter third-order intermodulation products (C-IM3). Also, using a Wilkinson combiner, the cross-coupling between two sub-SCPAs is isolated to enable a linear harmonic-rejection summation. With the proposed topology, the linearity is improved significantly compared to a conventional I/Q-sharing SCPA. More specifically, the C-IM3 is reduced by ~25 dB with a single-tone input and by ~22 dB with modulated signal.

This paper demonstrates a wideband 2.4 GHz$2\times 9$-bit Cartesian radio-frequency digital-to-analog converter (RFDAC). Active-under-coil integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely 0.35 mm2. An$8\times $analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in digital processing back-end. The multi-port transformer is adopted in the matching network to improve the back-off efficiency. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of that at the peak output power. The active-under-coil integration helps this RFDAC to achieve the smallest area among comparable prior arts.

An envelope elimination and restoration transmitter that comprises a class-E power amplifier (PA) and a digitally controlled current digital-to-analog converter (DAC) modulator are presented. A switched-capacitor DAC is designed to control an open-loop transconductor that operates as a current modulator, modulating the amplitude of the current supplied to a class-E PA. Such a topology allows for increased filtering of the quantization noise that is problematic in most digital PAs (DPA). The system measurements yield a peak output power and system efficiency (SE) of 22.5 dBm and 23.6%, respectively. When applying a local thermal equilibrium signal, the measured error vector magnitude is 3.72% and the adjacent channel leakage ratio is -30.2 dBc, while outputting 18.1 dBm at 10.6% SE.

An analog adaptive notch filter implementation at 54.1 MHz is presented in this paper. The analog circuit is implemented using discrete components. Implementation issues such as components phase shift and DC offset are discussed and solution for them are proposed. In addition, effect of frequency offset between reference and input signal is discussed. The implemented circuit has -3 dB bandwidth of 300 Hz and a null depth of 45 dB or better.

Piezoelectric microelectromechanical systems (MEMS) resonators on Si can be a potential candidate to replace discrete L-C components in series resonant converters. In this paper, ring shaped piezoelectric (AlN) micro-resonators on Si are reported. Having vibration in contour mode, these resonators can achieve resonant frequency as low as 87.28 MHz. Recently, we have fabricated high Q (>1000) piezoelectric resonator using a CMOS compatible fabrication process, and experimental characteristics of these devices are included in this paper. Contour mode AlN MEMS resonator with moderately low resonant frequency and motional resistance has been reported for the first time (the resonant frequency and motional resistance of the fabricated device is 87.28 MHz and 36.728 Ω respectively). Finally, an efficiency analysis of the series resonant topology has been performed using the equivalent electrical circuit model of the resonator.

As we are surrounded by an ever-larger variety of post-PC devices, the traditional methods for identifying and authenticating users have become cumbersome and time consuming. In this paper, we present a capacitive communication method through which a device can recognize who is interacting with it. This method exploits the capacitive touchscreens, which are now used in laptops, phones, and tablets, as a signal receiver. The signal that identifies the user can be generated by a small transmitter embedded into a ring, watch, or other artifact carried on the human body. We explore two example system designs with a low-power continuous transmitter that communicates through the skin and a signet ring that needs to be touched to the screen. Experiments with our prototype transmitter and tablet receiver show that capacitive communication through a touchscreen is possible, even without hardware or firmware modifications on a receiver. This latter approach imposes severe limits on the data rate, but the rate is sufficient for differentiating users in multiplayer tablet games or parental control applications. Controlled experiments with a signal generator also indicate that future designs may be able to achieve data rates that are useful for providing less obtrusive authentication with similar assurance as PIN codes or swipe patterns commonly used on smartphones today.

As we are surrounded by an ever-larger variety of post-PC devices, the traditional methods for identifying and authenticating users have become cumbersome and time-consuming. In this paper, we present a capacitive communication method through which a device can recognize who is interacting with it. This method exploits the capacitive touchscreens, which are now used in laptops, phones, and tablets, as a signal receiver. The signal that identifies the user can be generated by a small transmitter embedded into a ring, watch, or other artifact carried on the human body. We explore two example system designs with a low-power continuous transmitter that communicates through the skin and a signet ring that needs to be touched to the screen. Experiments with our prototype transmitter and tablet receiver show that capacitive communication through a touchscreen is possible, even without hardware or firmware modifications on a receiver. This latter approach imposes severe limits on the data rate, but the rate is sufficient for differentiating users in multiplayer tablet games or parental control applications. Controlled experiments with a signal generator also indicate that future designs may be able to achieve datarates that are useful for providing less obtrusive authentication with similar assurance as PIN codes or swipe patterns commonly used on smartphones today.

Today's identification and authentication mechanisms for touchscreen-enabled devices are cumbersome and do not support brief usage and device sharing. To address this challenge, this work explores a novel form of "wireless" communication that exploits the capacitive touchscreens which are now used in laptops, phones, and tablets, as a signal receiver. Using a custom built hardware token, in the form of a wearable ring, we show a proof-of-concept system that transmits a user identification code to the mobile device through the touchscreen. This mechanism works without any modification to the hardware or the firmware of the mobile device.

Body Sensor Networks (BSNs) consist of miniature sensors deployed on or implanted into the human body for health monitoring. Conserving the energy of these sensors, while guaranteeing a required level of performance, is a key challenge in BSNs. In terms of communication protocols, this translates to minimizing energy consumption while limiting the latency in data transfer. In this paper, we focus on polling-based communication protocols for BSNs, and address the problem of optimizing the polling schedule to achieve minimal energy consumption and latency. We show that this problem can be posed as a geometric program, which belongs to the class of convex optimization problems, solvable in polynomial time. We also introduce a dynamic priority vector for each sensor, based on the observation that relative priorities of sensors in a BSN change over time. This vector is used to develop a decision-tree based approach for resolving scheduling conflicts among devices. The proposed framework is applicable to a broad class of periodic polling-based communication protocols. We design one such protocol in detail and show that it achieves an improvement of approximately 45% over the widely accepted standard IEEE 802.15.4 MAC protocol.

A fully-integrated LNA in 0.18/xm CMOS simultaneously achieves high gain, low noise figure (NF), good third-order input intercept linearity (IIP3), and low DC bias current consumption: 19 dB, 2.4 dB, -14.2 dBm and 1.3 mA, respectively, from a 1.2 V supply. The single-ended LNA uses a common-gate common-source (CG-CS) topology and operates at 5.4 GHz for WLAN applications. Using gm-boosting, current-reuse and transformer-feedback techniques, the LNA mitigates several design issues seen in the widely used common-source common-source current-reuse (CS-CS) LNAs and improves the IIP3 of CG-CS schemes by 6 dB, without increasing power and area consumption.

An area-efficient U-shaped slow-wave coplanar waveguide (U-SCPW) in a standard 0.18 μm CMOS process is presented. Compared to a conventional straight line CPW (S-CPW), it provides a more compact layout because of its approximate 1:1 aspect ratio. Measured results show that it has a quality factor and phase velocity comparable to its straight-line counterpart with measured Q ~ 30 at 23 GHz.

A method to design spiral transformers is outlined. It utilizes simple inductance estimates in order to initially design the dimensions for the desired transformer, after which an EM simulation is used to extract s-parameters of the structure; a compact model is then extracted from the s-parameter results. A wideband compact model is proposed that is accurate up to the self-resonance frequency (SRF) of the structure. A 3-to-1 transformer is designed and its measured performance verified in a 0.18 μm RF CMOS process.