Online surrogate model-assisted evolution algorithms (SAEAs) are very efficient for analog/RF circuit optimization. To improve modeling accuracy/sizing results, we propose an efficient transfer learning-assisted global optimization (TLAGO) scheme that can transfer useful knowledge between neural networks to improve modeling accuracy in SAEAs. The novelty mainly relies on a novel transfer learning scheme, including a modeling strategy and novel adaptive transfer learning network, for high-accuracy modeling, and greedy strategy for balancing exploration and exploitation. With lower optimization time, TLAGO can have a faster rate of convergence and more than 8% better performances than GASPAD.

This paper proposes a two-step fine-tuning assisted layout sizing (FALS) scheme with an efficient post-layout sampling feature, the key of which is to reuse abundant and cheap schematic information with Transfer Learning for quickly pruning design space and achieving global optimization. The innovation is that FALS is the first work to integrate the advantages of two-step optimization and high-accuracy model-based local optimization. The same optimization results can be achieved by FALS with significantly 10× less total run-time than the conventional DE.

In recent years, electronic design automation methodologies based on hierarchical multilevel bottom-up (BU) design approaches are emerging and successfully applied for RF system design. In this article, we propose a design automation methodology for the synthesis of millimeter-wave (mm-wave) systems via BU approaches, including sizing and layout generation. First, uniformly sampled passive and active component libraries with prepared layouts and S-parameter files are constructed during the offline preparation stage. Second, the BU sizing from the device level to the system level has been demonstrated via multiobjective optimization algorithms, while an improved Euclidean mapping strategy is proposed to efficiently search over circuit-level Pareto-optimal fronts (POFs) in the system-level optimization. Third, the parameterized DRC/LVS clean layout can be hierarchically generated for the system-level POFs. Compared to flat optimization at the system level, the proposed method greatly reduces the size of the search space with the highest accuracy possible and can be used for the synthesis of complex mm-wave systems. The proposed method achieves a$10\times $runtime speedup in the system-level optimization with better optimization results.

This paper presents a fully integrated W-band multi-channel silicon-based radiometer array in a 65-nm CMOS process. Four channels are integrated to achieve higher resolution and sensitivity. A single channel consists of low noise amplifier (LNA), detector, and analog baseband (ABB), respectively. The four-stage LNA achieves a power gain of 29.9dB, a minimum noise figure (NF) of 5.0dB over the band of interest. The detector achieves responsivity of 2.34 kV/W and 23.9$\mathbf{pW}/\sqrt{\text{Hz}}$noise equivalent power (NEP). The radiometer achieves a responsivity of 42293 MV/W, an NEP of 0.21$\mathbf{fW}/\sqrt{\text{Hz}}$, and a temperature resolution (NETD) of 0.226 K with a 1 ms integration time. The total power consumption is 254.6 mW.

In this article, we propose an efficient surrogate-assisted constrained multiobjective evolutionary algorithm for analog circuit sizing via self-adaptive incremental learning. The proposed approach reduces the total optimization time in four aspects. First, by reusing the previously trained models, the incremental learning technique is introduced to reduce the time complexity of training the Kriging model from$O(n^{3})$to$O(n^{2})$, where$n$is the number of training points. Second, a self-adaptive strategy to control when to update hyperparameters is proposed to further reduce the training time of the Kriging model. Third, our method is driven by prescreening the most promising population instead of internal optimization which saves the prediction time of the Kriging model. Fourth, the maximin distance-based expected improvement matrix criterion is introduced as the acquisition function to formulate multiple objectives into a scalar function, reducing the sorting time to rank population. Experimental results on three real-world circuits demonstrate that compared with the state-of-the-art multiobjective Bayesian optimization, our method achieves a speedup of up to$13\times $in total runtime without surrendering optimization results. To be more specific, our method reduces the training time of the Kriging model by 96%, the prediction time by 99%, and the sorting time to rank population by up to 92%. Compared with NSGA-II, there is up to$6\times $speedup in terms of the total runtime with better results.

In this paper, we propose an efficient Kriging-based constrained multi-objective evolutionary algorithm for analog circuit synthesis via self-adaptive incremental learning. The incremental learning technique is introduced to reduce time complexity of training the Kriging model from$O(n^{3})$, to$O(n^{2})$, where$n$is the number of training points. The proposed approach reduces the total optimization time in three aspects. First, by reusing the previously trained models, a self-adaptive incremental learning strategy is applied to reduce the training time of the Kriging model. Second, we use non-dominated sorting and modified crowding distance to prescreen the most promising one to be simulated, which largely reduce the number of simulations. Third, as there is no internal optimization, the prediction time of the Kriging model is saved. Experimental results on two real-world circuits demonstrate that compared with the state-of-the-art multi-objective Bayesian optimization, our method can reduce the training time of Kriging model by 95% and the prediction time by 99.7% without surrendering optimization results. Compared with NSGA-II and MOEA/D, the proposed method can achieve up to 10X speed up in terms of the total optimization time while achieving better results.

The impact of process variation to advanced integrated circuits has become increasingly significant. Traditional sampling based yield analysis and optimization always require large amount of expensive simulations. This paper proposes an All Sensitivity Adversarial Importance Sampling (ASAIS) yield optimization method, which avoids samplings in outer optimization based on sensitivity. Moreover, Fast Sensitivity Importance Sampling (FSIS) yield analysis method is adopted as inner yield analysis to eliminate the sampling using transient sensitivity analysis. Experiments on SRAM show ASAIS generates more than 90X speedup of the entire yield optimization process, while FSIS speedup 3X-I5X over existing methods.

This paper presents a high-precision and energy-efficiency Capacitively-coupled Chopper Instrumentation amplifier (CCIA) for Wheatstone bridges readout. The Ripple Reduction Loop (RRL) structure is improved to enhance the attenuation effect. In addition, a novel Noise-Nonlinearity-Cancelling Loop (NNCL) is introduced to alleviate the noise contribution come from RRL. The power consumption of this part of circuit is ultra-low, so the whole amplifier still has a competitive Noise Efficiency factor (NEF). Switch-capacitor circuits and duty-cycled resistors are used respectively to improve the PVT robust stability of the design, where large resistors are demanded. The circuit is fully integrated in a 65- nm CMOS technology with a 1.0 mA current from a 1.8 V supply voltage. The CCIA achieves an input-referred noise density of 2.8 nV/√Hz and a NEF of 3.38.

In this paper, we propose a fractional-N PLL with charge pump linearization circuit to mitigate quantization noise fold-in and reference spur deterioration issues simultaneously. This linearization circuit with a novel clock gating technique can suppress the fold-in quantization noise to -110 dBc/Hz, without degrading the reference spur or incurring additional digital algorithm, and the power consumption is negligible, while prior arts either cause large reference spur due to strong instantaneous current mismatch or consume too much power. A process robust cascaded spur trapper is also proposed to guarantee at least an extra 20 dB attenuation of reference spur.

In this paper, we present a novel deep neural network (DNN) dedicated to dynamic gesture control based on a radio-frequency (RF) type sensors. The proposed network is based on auto-encoder (AE) and long short-term memory recurrent neural network (LSTM-RNN). The encoder for reduction and effective feature extraction is obtained by unsupervised training an AE with a large untagged RF database. Further a light LSTM network is trained use a small size of tagged datasets for dynamic gesture classification. Training the network with semi-supervised learning methods greatly reduces the requirement on the size of the tagged gestures datasets. Experimental results demonstrate that our AE-LSTM method outperforms existing networks in terms of accuracy and realizability. The proposed application is used for the human-computer interaction (HCI) of intelligent home, automatic driving and robot scenes.

This paper presents a fully-integrated 76-81 GHz four-channel digitally controlled receiver (RX) in 65-nm CMOS, which utilizes a four-channel RX front-end with high linearity, an LO distribution network, and a reconfigurable 4-channel analog baseband (ABB). It achieves high integration level and is capable of flexible reconfigurability automotive radars with wide and flattened temperature characteristic. Each RX front-end consists of a low noise amplifier (LNA) employing a neutralized common source (CS) with configurable high-linearity and an active mixer with linearity-priority design. Additionally, a bias circuit with positive temperature coefficient is used for temperature compensation of the millimeter wave (mm-Wave) amplifiers and mixer. The RX chain offers tunable gain and bandwidth (BW) with digital control and bandwidth tuning for the ABB. The measured results show that the RX achieves an input 1-dB compression point (Pin,1dB) of -7 dBm and a noise figure of 11-26 dB across a temperature range from -45 to +125°C, both over the range of 76-81 GHz. The RX has a tunable gain from 18 to 66 dB over the 3-dB programmable IF BW from 0.1 to 10 MHz. The power consumption of the entire receiver is 0.52 W.

Transient sensitivity is useful for analyzing the gradients of objective functions with respect to given parameters. This is useful in variation and circuit optimization. The computational complexity for traditional transient sensitivity analysis for objective function with N time points is O(N2), which is too expensive for large N. In this paper we propose a transient sensitivity analysis method that reduces the computational complexity to O(N), enabling the analysis of performance metrices related to thousands of time points, such as SNDR, THD, SFDR, and etc.

This paper presents a 20-Gb/s optical receiver consisting of a novel transimpedance amplifier (TIA), three active feedback Cherry-Hooper limiting amplifiers (LA) and DC offset cancellation loop. A novel cross-coupled dual-feedback loop TIA is proposed to reduce the input impedance and enhance the tolerance of large input capacitance without deterioration of the transimpedance gain. Moreover, not any extra noise, power consumption or chip area is introduced. Implemented in 65-nm CMOS technology, the receiver achieves 73.1 dBΩ transimpedance gain with a bandwidth of 10.2 GHz and a data rate of 20 Gb/s, while the input referred noise (IRN) current is below 30.5 pA/√Hz from 1 to 10.2 GHz. The core circuit consumes a DC power of 9.6 mW from a 1.2V supply (without output buffer) and occupies a layout area of 0.042 mm2.

This paper presents a 77 GHz Receiver (Rx) for automotive radar with high linearity, low noise figure (NF) and reconfigurable gain and bandwidth of the analog baseband (ABB), implemented in TSMC 65 nm CMOS general purpose (GP) technology. The Rx includes a low-noise amplifier (LNA), sharing the transconductance stage with a double-balanced mixer, an LO chain with a frequency doubler and an analog baseband. The entire Rx consumes 123 mW. Measurement results show that the input 1 dB compression point (P1dB) is -14 dBm at 81 GHz, a conversion gain (CG) of 20.5-62.5 dB is digitally tunable at 77 GHz, and an NF of 11.2-18.3 dB is achieved over the frequency range of 76-81 GHz.

Faster and more accurate variation characterizations of semiconductor devices/circuits are in great demand as process technologies scale down to Fin-FET era. Traditional methods with intensive data testing are extremely costly. In this paper, we propose a novel learning-based high-accuracy data prediction framework inspired by learning methods from computer vision to efficiently characterize variabilities of device/circuit behaviors induced by manufacturing process variations. The key idea is to adaptively learn the underlying data pattern among data with variations from a small set of already obtained data and utilize it to accurately predict the unmeasured data with minimum physical measurement cost. To realize this idea, novel regression modeling techniques based on Gaussian process regression and partial least squares regression with feature extraction and matching are developed. We applied our approach to real-time variation characterization for transistors with multiple geometries from a foundry 28nm CMOS process. The results show that the framework achieves about 14x time speed-up with on average 0.1% error for variation data prediction and under 0.3% error for statistical extraction compared to traditional physical measurements, which demonstrates the efficacy of the framework for accurate and fast variation analysis and statistical modeling.

This paper presents an accurate dB-linear programmable-gain amplifier with temperature-robust characteristic. A novel Gm-cell feedback topology is proposed to provide linear gain control as well as bandwidth extension without any extra power consumption. Moreover, a PTAT bias is employed to further promote the temperature robustness while AC coupling stages are embedded in the adjacent stages for DC-offset cancellation. Implemented in TSMC 65-nm CMOS technology, the proposed PGA exhibits a programmable gain range of 0 dB to 42 dB with 1 dB per step and 0.17 dB error. The gain variation across -40~125 °C is lower than 0.3 dB at all gain settings. The core circuit consumes a DC power of 3.8mV from a 1.2 V supply and occupies a layout area of 0.048 mm2.

This paper presents an automatic amplitude control (AAC) loop voltage controlled oscillator (VCO) with a constant VCO gain (Kvco) for fractional-N frequency synthesizers in WLAN application in 65nm CMOS process. A novel AAC scheme based on a mixed-signal feedback loop has been proposed to minimize the amplitude variation. In order to achieve a low Kvco variation, an extra switched varactor array is also introduced to the LC tank together with the conventional switched capacitor array. The VCO achieves a tuning range of 23.7% from 3.1 to 4.2GHz, while consuming 4.6mA of quiescent current from a 1.2V power supply. The peak amplitude variation over the entire frequency range is less than 10mV, which can be otherwise as large as 100mV, or 22.2% without the AAC loop. The VCO shows a nearly constant Kvco of 60MHz/V, a low phase noise of -123.3dBc/Hz at 1 MHz offset, and a superior FoM of -187dBc/Hz from a 3.6 GHz carrier.

Although automatic optimization for individual analog/RF modules has been studied for many years, design automation for analog/RF systems that contain a complicated hierarchy of mixed-signal modules is still very challenging as the lack of an efficient way to bridge between different level descriptions in the design hierarchy. In this paper, we applied sparse regression as a modeling tool to model the modules that need to be optimized and embedded the modules in a large system to accomplish a realistic 802.11ac system design. The wireless system specification (e.g. bit error rate) for comprehensively evaluating the analog/RF front-ends is used as the optimization objective. The proposed method is implemented by linking the block-level performance metrics to the wireless system using mixed-signal simulation platform with performance modeling and Pareto optimal fronts. By this method, the receiver for 802.11ac systems is successfully designed and the worst error vector magnitude (EVM) is decreased by 34% from coarse design.

In this paper, a fully integrated 24GHz integer-N PLL for a 60GHz wireless transceiver is presented. A VCO with tail-feedback technique is used to improve the phase noise by modulating the tail current, and a switched varactor array is also adopted together with a switched capacitor array to compensate the variation of KVCOover different bands. Moreover, benefiting from the careful optimization of CML pre-scaling divider, the PLL operates correctly when VCO buffer is turned off, coming up with an extremely low power. The whole PLL is fabricated in standard 90-nm process. Measurement shows that the VCO achieves a phase noise of -102dBc/Hz@1MHz offset with a tuning range of over 16%. The KVCOvariation over all bands is less than 16%. In close-loop operation mode the PLL shows an integrated phase error of 3.3°rms (from 100kHz to 100MHz) over prescribed frequency bands, and a total power dissipation of only 26mW.

A 60GHz receiver for 802.11ad application with superior performance in 90nm CMOS process, compared with prior arts in advanced processes, is proposed and realized. A 3-stage differential LNA achieves a gain of 19.8dB and a noise figure of 6dB in measurement, showing less than 0.3dB difference from simulation due to the elaborate consideration of parasitics. A baseband PGA with wideband and large gain tuning range is achieved from modified Cherry-Hooper amplifier with negative capacitive neutralization technique. The entire receiver achieves a double-side-band NF of 7.1dB and a maximal conversion gain of 64dB with 28dB tuning range, while consuming only 177mW of power. The measured output P1dBis -5.5dBm. All measured results are rigorously loyal to the simulation.

A 0.0015-mm$^{2}~1.28$-mW single-branch analog equalizer is demonstrated in 65-nm CMOS for 10-Gb/s input/output links. Instead of using passive inductors that are untunable and unscalable with technologies, gain compensation here is optimized via a tunable and current-reusable active inductor (AI). This AI incorporates a positive-feedback impedance converter with only two MOSFETs and one MOS varactor. Together with the use of: 1) negative Miller capacitors to optimize the pole-zero composition and 2) tunable resistive source degeneration to adjust the low-frequency losses, the analog equalizer recovers an eye-opening rate of minimally 30% up to 10 Gb/s over a pair of 60-cm FR4 microtrip traces. The data Pk-to-Pk jitter is$2^{7}$–1,$2^{15}$–1, and$2^{31}$–1).

SRAM cells usually require extremely low failure rate or equivalently extremely high production yield, making it impractical to perform yield analysis using Monte Carlo (MC) method as huge amount of samples are needed. Fast MC methods, e.g., importance sampling methods, are still too expensive as the anticipated failure rate is very low. In this paper, a new SRAM yield analysis method is proposed to tackle this issue. The key idea is to improve traditional importance sampling method with an efficient online surrogate model. Experimental results show that the proposed yield analysis method achieves $5\times $ -$22\times $ speedup over existing state-of-the-art techniques without sacrificing estimation accuracy. Sigma distribution and schmoo plot can be quickly generated by the proposed method, which is very useful for realistic applications. Based on the proposed yield analysis method, an efficient yield optimization method has been developed to further automate the SRAM cell design procedure where process variations can be fully considered. Experimental results show that a fully automatic yield optimization for SRAM cells can be done within only a few hours.

High-sigma analysis is important for estimating the probability of rare events. Traditional high-sigma analysis can only work for small-size (low-dimension) problems limiting to 10 ~ 20 random variables, mostly due to the difficulty of finding optimal boundary points. In this paper we propose an efficient method to deal with high-dimension problems. The proposed method is based on performing optimization in a series of low dimension parameter spaces. The final solution can be regarded as a greedy version of the global optimization. Experiments show that the proposed method can efficiently work with problems with > 100 independent variables.

SRAM cells generally require an extremely low failure rate (i.e., high yield) in the per cell basis to ensure a reasonably moderate yield for the whole chip. Existing yield analysis methods still encounter issues related to multiple failure regions resulting from high-dimensional process parameter space and/or multiple performance specifications. This paper proposes a new method that combines the advantages of existing importance sampling and boundary searching methods, and avoids issues in both. The key idea is to first find all likely failure regions and then, do importance sampling on these regions. Surrogate models are used to further accelerate the method so that SPICE-simulations can be highly reduced. Experimental results show that the proposed method is suitable for handling problems with multiple failure regions. Meanwhile, it can provide 5X ~ 20X speed-up over other existing techniques.

Scalable compact models for passive elements are important in the Analog/RF circuit design and optimization. Traditional scalable modeling methods are mainly physical and manual based methods, which usually require deep physical insight and extensive human intervention. In this paper, an automatic scalable compact modeling method for generic passive elements is established. The proposed method is a unified parameter extraction and scalable modeling scheme with novel inner-loop correlated parameter extraction and outer-loop adaptive boundary compression techniques. Experimental results show that both accuracy and scalability have been achieved by the proposed method for industrial inductors and transformers with an acceptable computational cost.

Finer grid representation is required for a more accurate description of mask patterns in inverse lithography techniques, thus resulting in a large-size mask representation and heavy computational cost. To mitigate the computation problem caused by intensive convolutions in mask optimization, a new method called convolution using basis expansion (CBE) is discussed in this paper. Matrices defined in fine grid are projected on coarse gird under a base matrix set. The new matrices formed by the expansion coefficients are used to perform convolution on the coarse grid. The convolution on fine grid can be approximated by the sum of a few convolutions on coarse grid following an interpolation procedure. The CBE is verified by random matrix convolutions and intensity calculation in lithography simulation. Results show that the use of the CBE method results in similar image quality with significant running speed enhancement compared with traditional convolution method.

Massively repeated structures such as SRAM cells usually require extremely low failure rate. This brings on a challenging issue for Monte Carlo based statistical yield analysis, as huge amount of samples have to be drawn in order to observe one single failure. Fast Monte Carlo methods, e.g. importance sampling methods, are still quite expensive as the anticipated failure rate is very low. In this paper, a new method is proposed to tackle this issue. The key idea is to improve traditional importance sampling method with an efficient online surrogate model. The proposed method improves the performance for both stages in importance sampling, i.e. finding the distorted probability density function, and the distorted sampling. Experimental results show that the proposed method is 1e2X∼1e5X faster than the standard Monte Carlo approach and achieves 5X∼22X speedup over existing state-of-the-art techniques without sacrificing estimation accuracy.

In this paper, a wide-band inductor-less LNA for low voltage operation is presented. The input matching is implemented by using a feedback transistor with a resistor terminated to the source to enhance linearity and to reduce noise. Current reuse technique is employed to increase the total transconductance. Under 1V supply voltage and a DC of 5.6 mA, the LNA achieves an average noise figure of 3.2 dB, a maximum voltage gain of 18.6 dB, and 3 dB bandwidth ranges from 0.2-4.5 GHz.

Phase noise of oscillators can be improved through noise filtering. This paper presents a transformer-based harmonic filtering technique to improve the phase noise performance of the fully differential CMOS LC oscillators. The primary and secondary of the transformer are placed at the sources of NMOS and PMOS differential pairs, respectively. Due to the extra degree of freedom introduced by the transformer, the filter can resonate at two different frequencies, which are designed to be the second and fourth harmonics. The analysis of the filtering method is presented and principles of operation are discussed in details. The performance is compared with other filtering techniques, and the simulation results show improved FoM compared to published literature.

Power consumption has become a major concern since the integrated circuit industry entered the nanometer design regime. Due to the increasing process variation, deterministic leakage power analysis becomes inadequate and thus statistical analysis is required. The challenges of statistical leakage analysis are that the huge number of random variables make trivial computation of the variance inO(N2) time impractical for realistic designs and that knowing only the first two moments is not sufficient to obtain the distribution of the full-chip leakage. In this paper, we introduce efficient linear time algorithms for statistical leakage analysis. To enable those algorithms, a fast matrix vector product technique is crucial, being applied not only to compute the second moment of the total leakage, but also, combined with a comonotonic approximation, to estimate the distribution function of the total leakage power. The computational complexity of the proposed algorithms is provablyO(N), and the experimental result is presented with detailed discussion, indicating promising improvement in terms of accuracy.

Random process variations are often composed of location dependent part and distance dependent correlated part. While an accurate extraction of process variation is a prerequisite of both process improvement and circuit performance prediction, it is not an easy task to characterize such complicated spatial random process from a limited number of silicon data. For this purpose, kriging model was introduced to silicon society. This work forms a modified kriging model with L1-norm penalty which offers improved robustness. With the help of Least Angle Regression (LAR) in solving a core optimization sub-problem, this model can be characterized efficiently. Some promising results are presented with numerical experiments where a 3X improvement in model accuracy is shown.

This paper presents a full ESD-protected receiver front-end for wireless communications around 24GHz, comprising LNA, mixer, VGA, and on-chip balun. A π -type input matching network incorporating ESD capacitance is constructed to realize the source impedance transformation for higher gain. With it, the gain of the first stage is improved while the noise figure is just degraded slightly. The measured results show an input return loss of less than-12dB, 36dB voltage gain, 6.9dB noise figure, and 2dBm output P1dB. The chip has an HBM ESD robustness of ± 2kV and consumes 34mA from a 1.2V supply with a total area of 1×0.8 mm2using 0.13μm RF CMOS process.

An analytical framework has been developed to describe the locking behavior of millimeter (mm) wave current mode logic (CML) frequency divider. Unlike traditional analysis based on RC delay, the proposed model is established with injection-locking concept from analog perspective. Both analytical formulas and graphic interpretation are provided for design insights. The model has been validated by exhaustive simulations and important guidelines have been concluded for circuit design.

Source and mask optimization (SMO) has been proposed recently as an effective solution to extend the lifespan of conventional 193 nm lithography, although the process is computationally intensive. In this study, we propose a highly effective and efficient method for source optimization and improve a previous method for mask optimization. An SMO framework is implemented by integrating them. Based on pixel-based source and mask representation, the gradients of the objective function are utilized to guide optimization. In addition to maintain the image fidelity, extra penalties are added into the objective function to increase the depth of focus (DOF) and regularize the source and mask patterns. In our SMO framework, a specially designed mask optimization procedure is performed to enhance the algorithm robustness. Afterward, the source optimization and mask optimization are performed alternatively. Convergence results can be acquired using only two or three iteration cycles. This method is demonstrated using two mask patterns with critical dimensions of 45 nm, including a periodic array of contact holes and a cross gate design. The results show that our method can provide great improvements in both image quality and DOF. The robustness of our method is also verified using different initial conditions.

A robust pixel-based optimization algorithm is proposed for mask synthesis of inverse lithography technology (ILT) to improve the resolution and pattern fidelity in optical lithography. Result shows that the final image fidelity is almost independent of the initial condition. To demonstrate the robustness of the algorithm, six typical desired mask patterns and two mask technologies are applied in mask synthesis optimization using 100 randomly generated initial conditions. The critical dimension (CD) is 60nm and the partial-coherence image system is applied. It is found that the final edge placement error (EPE) and iteration number are quite weakly dependent on the initial conditions. Good final image fidelity can be acquired using arbitrary initial conditions. This algorithm is about several orders of magnitude faster and more effective than other gradient-based algorithm and simulated annealing algorithm.

Existing approaches to statistical leakage analysis focus only on calculating the mean and variance of the total leakage. In practice, however, what concerns most is the tail behavior of the sum distribution, as it tells that to what extent the design will be safe or reliable. However, computing the tail distribution is much more difficult than computing the mean and variance. In this paper, we tackle this problem by making use of the recent developments in the area of financial and insurance analysis, as well as the fast evaluation algorithm for the variance of spatially correlated random sums. The proposed algorithm is provably of O(N) complexity. Experiments show that the algorithm provides 1% accuracy in modeling the tail behavior and it is 10X more accurate compared with existing methods that approximate the distribution by matching the moments of a lognormal distribution.

An efficient algorithm based on the pixel-based mask representation is proposed for fast synthesis of model-based inverse lithography technology (ILT) to improve the resolution and pattern fidelity in optical lithography. This new algorithm reduces N2intensity computations to three (3) equivalent intensity computations per iteration, where N2is the total number of pixels in a mask. This algorithm has been demonstrated using different critical dimensions (CDs) and different mask technologies with incoherence and partial-coherence image models. This algorithm is about 60 times faster and more effective than the current gradient-based algorithm. The final image fidelity has quite a weak dependence on the initial condition. Good fidelity images are achieved when CD is reduced to 45 nm.